AK4392 Datasheet, PDF (22/41 Pages) Asahi Kasei Microsystems – High Performance 120dB Premium 32-Bit DAC

[AK4392]
[3] External Digital Filter Mode (EX DF I/F Mode)
DW indicates the number of BCK in one WCK cycle. The audio data is input by MCLK, BCK and WCK from the DINL
and DINR pins. Three formats are available (Table 9) by DIF2-0 bits setting. The data is latched on the rising edge of
BCK. The BCK and MCLK clocks must be the same frequency and must not burst. BCK and MCLK frequencies for each
sampling speed are shown in Table 8.
The AK4392 is automatically placed in reset state when MCLK and WCK are stopped during a normal operation (PDN
pin =“H”), and the analog output becomes Hi-Z. When MCLK and WCK are input again, the AK4392 exit reset state and
starts the operation. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations, the AK4392 is in
power-down mode until MCLK and WCK are supplied.
Sampling
Speed[kHz]
128fs
192fs
MCLK&BCK [MHz]
256fs
384fs
512fs
WCK
ECS
768fs
44.1(30~54)
N/A
N/A
N/A
N/A
22.5792
33.8688
16fs
0
32
48
DW
44.1(30~54)
N/A
N/A
11.2896 16.9344
N/A
33.8688
8fs
1
32
48
96
DW
96(54~108)
N/A
N/A
24.576
36.864
N/A
N/A
8fs
0
32
48
DW
96(54~108)
12.288
18.432
N/A
36.864
N/A
N/A
4fs
1
32
48
96
DW
192(108~216)
24.576
36.864
N/A
N/A
N/A
N/A
4fs
0
32
48
DW
192(108~216)
N/A
36.864
N/A
N/A
N/A
N/A
2fs
1
96
DW
Table 8 System Clock Example (EX DF I/F mode) (N/A: Not available)
Mode DIF2 DIF1 DIF0
Input Format
0
0
0
0 16bit LSB justified
1
0
0
1
N/A
2
0
1
0
N/A
3
0
1
1
N/A
4
1
0
0 24bit LSB justified
5
1
0
1 32bit LSB justified
6
1
1
0
N/A
7
1
1
1
N/A
Table 9 Audio Interface Format (EX DF I/F mode) (N/A: Not available)
MS1045-E-02
- 22 -
2009/04