DSP16410C Datasheet, PDF (95/373 Pages) Agere Systems – DSP1629 Digital Signal Processor

Data Sheet
June 2001
DSP16410B Digital Signal Processor
4 Hardware Architecture (continued)
4.5 Memory Maps (continued)
4.5.4 X-Memory Map
0x00000
0x17FFF
0x1FFC0
0x1FFFD
0x20000
0x20FFF
XMAP
TPRAMn (PRIVATE^†)
96 Kwords
RESERVED
CACHEn (PRIVATE^†)
62 words
RESERVED
IROMn (PRIVATE^†)
4 Kwords
0x18000
0x1FFBF
0x1FFFE
0x1FFFF
0x21000
0x80000
RESERVED
INTERNAL
0x7FFFF
EXTERNAL
EROM (SHARED)^‡
0xFFFFF
16 bits
† n is 0 for CORE0 or 1 for CORE1. Private memory can be accessed by the core with which it is associated. TPRAM0, CACHE0, and IROM0
cannot be accessed directly by CORE1. TPRAM1, CACHE1, and IROM1 cannot be accessed directly by CORE0. Both TPRAM0 and
TPRAM1 can be accessed by the DMAU and PIU.
‡ EROM can be configured as four glueless 512 Kword (1 Mbyte) segments or one 8 Mword (16 Mbytes) segment. See Section 4.14.4.3 begin-
ning on page 111 for details. EROM is shared, i.e., it is accessible by both CORE0 and CORE1, and it is also accessible by the DMAU and the
PIU.
Figure 6. X-Memory Map
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