DSP16410C Datasheet, PDF (47/373 Pages) Agere Systems – DSP1629 Digital Signal Processor

Data Addendum
May 2001
DSP16410C Digital Signal Processor
8 Timing Characteristics and Requirements (continued)
8.11 SIU (continued)
SICK
t45
t46
t47
SIFS
t48
t49
SID
B0
B1
B2
B0
t50
5-8029 (F)
Note: It is assumed that the SIU is configured with ICKA(SCON10[2]) = 1 for active mode input clock, ICKK(SCON10[3]) = 0 for no inversion of
SICK, IFSA(SCON10[0]) = 1 for active mode input frame sync, IFSK(SCON10[1]) = 0 for no inversion of SIFS, IMSB(SCON0[2]) = 0 for
LSB-first input, and IFSDLY[1:0](SCON1[9:8]) = 00 for no input frame sync delay.
Figure 30. SIU Active Frame and Channel Mode Input Timing Diagram
Table 49. Timing Requirements for SIU Active Frame Mode Input
Abbreviated
Reference
t45
t49
t50
Parameter
SICK Bit Clock Period (high to high)
SID Setup Time (valid to low)
SID Hold Time (low to invalid)
Min
Max
Unit
25^†
—
ns
9
—
ns
8
—
ns
† The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the AGEXT field (SCON12[12]). The
period of SICK is dependent on the period of the active clock source and the programming of the AGCKLIM[7:0] field (SCON11[7:0]). The
application must ensure that the period of SICK is at least 25 ns.
Table 50. Timing Characteristics for SIU Active Frame Mode Input
Abbreviated
Reference
t46
t47
t48
Parameter
SICK Bit Clock High Time (high to low)
SICK Bit Clock Low Time (low to high)
SIFS Delay (high to high)
Min
TAGCKH^† – 3
TAGCKL^† – 3
TCKAG^† – 5
Max
Unit
TAGCKH^† + 3 ns
TAGCKL^† + 3 ns
TCKAG^† + 5
ns
† TAGCKH and TAGCKL are dependent on the programming of the AGCKLIM[7:0] field (SCON11[7:0]) and the period of the active clock source.
TCKAG is the period of the active clock source. The active clock source is programmed as either the internal clock CLK or the SCK pin,
depending on the AGEXT field (SCON12[12]).
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