DSP16410C Datasheet, PDF (253/373 Pages) Agere Systems – DSP1629 Digital Signal Processor

Data Sheet
June 2001
DSP16410B Digital Signal Processor
4 Hardware Architecture (continued)
4.17 Internal Clock Selection
The DSP16410B internal clock can be driven from one
of two sources. The primary source clock is an on-chip
programmable clock synthesizer that can be driven by
an external clock input pin (CKI) at a fraction of the
required instruction rate. The clock synthesizer is
based on a phase-lock loop (PLL). The terms clock
synthesizer and PLL are used interchangeably.
Section 4.18 describes the PLL and its associated
pllcon, pllfrq, and plldly registers in detail.
Note: Internal clock functions for the DSP16410B are
controlled by CORE0 because the registers
pllcon, pllfrq, and plldly are only available to
programs executing in CORE0.
Figure 54 illustrates the internal clock selection logic
that selects the internal clock (fCLK) from one of the fol-
lowing two source clocks:
„ CKI: This pin is driven by an external oscillator or the
pin’s associated boundary-scan logic under JTAG
control. If CKI is selected as the source clock, fCLK
has the frequency and duty cycle of fCKI. The
DSP16410B consumes less power if clocked with
CKI.
„ PLL: The PLL generates a source clock with a pro-
grammable frequency. If the PLL is selected as the
source clock, fCLK has the frequency and duty cycle
of the PLL output fSYN.
After device reset, the default source clock signal is
CKI.
The programmer can select the PLL as the source
clock by setting the PLLSEL field (pllcon[0]—see
Table 122 on page 199). Before selecting the PLL as
the clock source, the user program must first enable
(power up) the PLL by setting the PLLEN field
(pllcon[1]) and then wait for the PLL to lock. See
Section 4.18 for details.
Table 121 summarizes the selection of the two source
clocks as a function of the PLLSEL field.
Table 121. Source Clock Selection
PLLSEL
(pllcon[0])
0
1
fCLK
fCKI
fSYN
Description
CKI pin
PLL
Internal Clock Selection Logic
PLLSEL
(pllcon[0])
CKI
fCKI
0
SYNC
MUX^†
fCLK
CLK
1
fCKI
fPLL
PLL
PLLEN
(pllcon[1])
CLOCK SELECTION LOGIC
† The multiplexer is designed so that no partial clocks or glitching occurs.
Figure 54. Internal Clock Selection Logic
Agere Systems Inc.
Agere Systems—Proprietary
197
Use pursuant to Company instructions