DSP16410C Datasheet, PDF (45/373 Pages) Agere Systems – DSP1629 Digital Signal Processor

Data Addendum
May 2001
DSP16410C Digital Signal Processor
8 Timing Characteristics and Requirements (continued)
8.11 SIU (continued)
SOCK
t37
t38
t39
SOFS
t41
t40
SOD
t42
B0
B1
t41
t44
t40
B0
B1
Note:
t43
5-8032 (F)
It is assumed that the SIU is configured with OCKA(SCON10[6]) = 0 for passive mode output clock, OCKK(SCON10[7]) = 0 for no inver-
sion of SOCK, OFSA(SCON10[4]) = 0 for passive mode output frame sync, OFSK(SCON10[5]) = 0 for no inversion of SOFS,
OMSB(SCON0[10]) = 0 for LSB-first output, OFRAME(SCON2[7]) = 0 for channel mode output, and OFSDLY[1:0](SCON2[9:8]) = 00 for
no output frame sync delay.
Figure 28. SIU Passive Channel Mode Output Timing Diagram
Table 46. Timing Requirements for SIU Passive Channel Mode Output
Abbreviated Reference
t37
t38
t39
t40
t41
Parameter
SOCK Bit Clock Period (high to high)
SOCK Bit Clock High Time (high to low)
SOCK Bit Clock Low Time (low to high)
SOFS Hold Time (high to low or high to high)
SOFS Setup Time (low to high or high to high)
Table 47. Timing Characteristics for SIU Passive Channel Mode Output
Abbreviated Reference
t42
t43
t44
Parameter
SOD Delay (high to valid)
SOD Hold (high to invalid)
SOD Deactivation Delay (high to 3-state)
Min
61.035
28
28
10
10
Min
1
0
—
Max
—
—
—
—
—
Max
16
4
12
Unit
ns
ns
ns
ns
ns
Unit
ns
ns
ns
Agere Systems Inc.
45