DSP16410C Datasheet, PDF (101/373 Pages) Agere Systems – DSP1629 Digital Signal Processor

Data Sheet
June 2001
DSP16410B Digital Signal Processor
4 Hardware Architecture (continued)
4.8 Interprocessor Communication
Effective interprocessor (core-to-core) communication
requires synchronization and access to required data.
The following hardware mechanisms support access
synchronization:
„ The MGU provides core-to-core interrupts and traps.
„ The MGU provides message buffer interrupts and
flags.
„ DMAU interrupts.
The following mechanisms support data access:
„ The MGU can control the occurrence of a synchro-
nizing event (interrupt/trap) for information/status
transfer.
„ The MGU provides data transfer through its full-
duplex message buffers (mgi and mgo).
„ The DMAU can copy data from one core’s TPRAM to
the other core’s TPRAM.
„ Cores can directly share data in external memory
(ERAM, EROM, or EIO spaces).
„ Cores can directly share data in the SLM.
Figure 12 illustrates the interprocessor communication
logic provided by MGU0 and MGU1.
Inter-Processor Communication Logic in MGU0 and MGU1
CORE0
FLAGS
INTERRUPTS
MGOBF MGIBE MGIBF XIO SIGINT PTRAP
CORE1
INTERRUPTS
FLAGS
PTRAP SIGINT XIO MGIBF MGIBE MGOBF
BIT 1 BIT 0
signal
mgi
mgo
MGU0
pid
imux
2
imux
2
MUX
2
0
IMUX0
MUX
2
0
IMUX1
BIT 0 BIT 1
signal
16
16
pid
mgi
mgo
MGU1
TRAP
DMINT[5:4]
(INTERRUPTS
FROM DMAU)
KEY:
PROGRAM-ACCESSIBLE REGISTERS
Figure 12. Interprocessor Communication Logic in MGU0 and MGU1
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