DSP16410C Datasheet, PDF (300/373 Pages) Agere Systems – DSP1629 Digital Signal Processor

DSP16410B Digital Signal Processor
Data Sheet
June 2001
6 Software Architecture (continued)
6.2 Registers (continued)
6.2.3 Register Encodings (continued)
Table 161. timer0c and timer1c (TIMER〈0,1〉 Control) Registers
15—7
Reserved
6
PWR_DWN
5
RELOAD
4
COUNT
3—0
PRESCALE[3:0]
Bit
Field
Value
Description
R/W Reset
Value
15—7
Reserved
0 Reserved—write with zero.
R/W
0
6
PWR_DWN
0 Power up the timer.
R/W
0
1 Power down the timer^†.
5
RELOAD
0 Stop decrementing the down counter after it reaches zero.
R/W
0
1 Automatically reload the down counter from the period register after
the counter reaches zero and continue decrementing the counter
indefinitely.
4
COUNT
0 Hold the down counter at its current value, i.e., stop the timer.
R/W
0
1 Decrement the down counter, i.e., run the timer.
3—0 PRESCALE[3:0]
0000
0001
0010
0011
Controls the counter prescaler to determine the fre-
quency of the timer, i.e., the frequency of the clock
applied to the timer down counter. This frequency is a
ratio of the internal clock frequency fCLK.
fCLK/2
fCLK/4
fCLK/8
fCLK/16
R/W 0000
0100
fCLK/32
0101
fCLK/64
0110
fCLK/128
0111
fCLK/256
1000
fCLK/512
1001
fCLK/1024
1010
fCLK/2048
1011
fCLK/4096
1100
fCLK/8192
1101
fCLK/16384
1110
fCLK/32768
1111
fCLK/65536
† If TIMER〈0,1〉 is powered down, timer〈0,1〉 cannot be read or written. While the timer is powered down, the state of the down counter and period regis-
ter remain unchanged.
244
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Agere Systems Inc.
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