DSP16410C Datasheet, PDF (33/373 Pages) Agere Systems – DSP1629 Digital Signal Processor

Data Addendum
May 2001
DSP16410C Digital Signal Processor
8 Timing Characteristics and Requirements (continued)
8.9 System and External Memory Interface (continued)
8.9.1 Asynchronous Interface
ECKO^{† VOH–}
VOL–
EREQN
ED
EA
t122
t122
t123
t129
t127
ENABLES
EACKN
t128
t125
t124
† ECKO reflects CLK, i.e., ECON1[1:0] = 1.
Figure 16. Timing Diagram for EREQN and EACKN
Table 25. Timing Requirements for EREQN
Abbreviated
Parameter
Min
Reference
t122
EREQN Setup (low to high or high to high)
t129
EREQN Deassertion (high to low)
5
ATIMEMAX^†
† ATIMEMAX = the greatest of IATIME(ECON0[11:8]), YATIME (ECON0[7:4]), and XTIME (ECON0[3:0]}.
Max
—
—
Unit
ns
ns
Table 26. Timing Characteristics for EACKN and SEMI Bus Disable
Abbreviated
Reference
t123
t124
t125
t127
t128
Parameter
Memory Bus Disable Delay (high to 3-state)
EACKN Assertion Delay^† (high to low)
EACKN Deassertion Delay (high to high)
Memory Bus Enable Delay (high to active)
EACKN Delay (high to low)
Min
Max
—
6
4T^‡
—
4T^‡
4T^‡ + 3
5
—
—
3
Unit
ns
ns
ns
ns
ns
† If any ENABLE is asserted (low) when EREQN is asserted (low), then the delay occurs from the time that ENABLE is deasserted (high).
(The SEMI does not acknowledge the request by asserting EACKN until it has completed any pending memory accesses.)
‡ T = internal clock period (CLK).
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