DSP16410C Datasheet, PDF (358/373 Pages) Agere Systems – DSP1629 Digital Signal Processor

DSP16410B Digital Signal Processor
Data Sheet
June 2001
11 Timing Characteristics and Requirements (continued)
11.11 SIU (continued)
SOCK
t51
t52
t53
SOFS
SOD
t55
B0
B1
B2
t56
t54
B0
5-8030 (F)
Note:
It is assumed that the SIU is configured with OCKA(SCON10[6]) = 1 for active mode output clock, OCKK(SCON10[7]) = 0 for no inver-
sion of SOCK, OFSA(SCON10[4]) = 1 for active mode output frame sync, OFSK(SCON10[5]) = 0 for no inversion of SOFS,
OMSB(SCON0[10]) = 0 for LSB-first output, OFRAME(SCON2[7]) = 1 for frame mode output, and OFSDLY[1:0](SCON2[9:8]) = 00 for
no output frame sync delay.
Figure 91. SIU Active Frame Mode Output Timing Diagram
Table 224. Timing Requirements for SIU Active Frame Mode Output
Abbreviated Reference
Parameter
t51
SOCK Bit Clock Period (high to high)
Min Max Unit
25^†
—
ns
† The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the AGEXT field (SCON12[12]). The
period of SOCK is dependent on the period of the active clock source and the programming of the AGCKLIM[7:0] field (SCON11[7:0]). The
application must ensure that the period of SOCK is at least 25 ns.
Table 225. Timing Characteristics for SIU Active Frame Mode Output
Abbreviated Reference
t52
t53
t54
t55
t56
Parameter
SOCK Bit Clock High Time (high to low)
SOCK Bit Clock Low Time (low to high)
SOFS Delay (high to high)
SOD Data Delay (high to valid)
SOD Data Hold (high to invalid)
Min
TAGCKH^† – 3
TAGCKL^† – 3
TCKAG^† – 5
0
–3
Max
TAGCKH^† + 3
TAGCKL^† + 3
TCKAG^† + 5
16
5
Unit
ns
ns
ns
ns
ns
† TAGCKH and TAGCKL are dependent on the programming of the AGCKLIM[7:0] field (SCON11[7:0]) and the period of the active clock source.
TCKAG is the period of the active clock source. The active clock source is programmed as either the internal clock CLK or the SCK pin,
depending on the AGEXT field (SCON12[12]).
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