DSP16410C Datasheet, PDF (289/373 Pages) Agere Systems – DSP1629 Digital Signal Processor

Data Sheet
June 2001
DSP16410B Digital Signal Processor
6 Software Architecture (continued)
6.2 Registers (continued)
6.2.3 Register Encodings (continued)
Table 141. auc0 (Arithmetic Unit Control 0) Register
15—14
P1SHFT[1:0]
13—11
Reserved
10
9
8
7
6
FSAT SHFT15 RAND X=Y= YCLR
5—4
ACLR[1:0]
3—2
ASAT[1:0]
1—0
P0SHFT[1:0]
Bit
Field
Value
Description
R/W
15—14 P1SHFT[1:0] 00 p1 not shifted.
R/W
01 p1>>2.
10 p1<<2.
11 p1<<1.
13—11
Reserved
0 Reserved—write with zero.
R/W
10
FSAT
0 Disabled when zero.
R/W
1 Enable 32-bit saturation for the following results: the scaled out- R/W
puts of the p0 and p1 registers, the intermediate result of the
3-input ADDER^†, and the results of the ALU/ACS, ADDER/ACS,
and BMU.
9
SHFT15
0 p1>>15 in F1E operations performs normally.
R/W
1 To support GSM-EFR, p1>>15 in F1E operations actually per-
forms (p1>>16)<<1 clearing the least significant bit.
8
RAND
0 Enable pseudorandom sequence generator (PSG).^‡
R/W
1 Reset and disable pseudorandom sequence generator (PSG).
7
X=Y=
0 Normal operation.
R/W
1 Data transfer statements that load the y register also load the x
register with the same value.^§
6
YCLR
0 The DAU clears yl if it loads yh.
R/W
1 The DAU leaves yl unchanged if it loads yh.
5
ACLR[1]
0 The DAU clears a1l if it loads a1h.
R/W
1 The DAU leaves a1l unchanged if it loads a1h.
4
ACLR[0]
0 The DAU clears a0l if it loads a0h.
R/W
1 The DAU leaves a0l unchanged if it loads a0h.
3
ASAT[1]
0 Enable a1 saturation^†† on 32-bit overflow.
R/W
1 Disable a1 saturation on 32-bit overflow.
2
ASAT[0]
0 Enable a0 saturation^†† on 32-bit overflow.
R/W
1 Disable a0 saturation on 32-bit overflow.
1—0
P0SHFT[1:0] 00 p0 not shifted.
R/W
01 p0>>2.
10 p0<<2.
11 p0<<1.
Reset
Value
00
0
0
0
0
0
0
0
0
0
0
0
00
† Saturation takes effect only if the ADDER has three input operands and there is no ALU/ACS operation in the same instruction.
‡ After re-enabling the PSG by clearing RAND, the program must wait one instruction cycle before testing the heads or tails condition.
§ The following apply:
„ Instructions that explicitly load any part of the x register (i.e., x, xh, or xl) take precedence over the X=Y= mode.
„ Instructions that load yh (but not x or xh) load xh with the same data. If YCLR is zero, the DAU clears yl and xl.
„ Instructions that load yl load xl with the same data and leave yh and xh unchanged.
†† If enabled, 32-bit saturation of the accumulator value occurs if the DAU stores the value to memory or to a register. Saturation also applies if the DAU
stores the low half, high half, or guard bits of the accumulator. There is no change to the contents stored in the accumulator; only the value stored to
memory or a register is saturated.
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