DSP16410C Datasheet, PDF (278/373 Pages) Agere Systems – DSP1629 Digital Signal Processor

DSP16410B Digital Signal Processor
Data Sheet
June 2001
6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
Table 133. F1E Function Statement Syntax (continued)
xh = aSPEh + yh
xh = aSPEh – yh
ALU^†
xl = aSPEl + yl^††
xl = aSPEl – yl^††
Special-Purpose MAC Function Statements for Viterbi
ADDER^†
aDE = aSEE + p0 + p1
p0 = xh**2
aDE = aSEE + p0 + p1
p0 = xh**2
aDE = aSE + p0 + p1^‡
p0 = xh**2
Multipliers
p1 = xl**2
p1 = xl**2
p1 = xl**2
ALU^†
aDEE = –aSEE + p0
Special-Purpose MAC Function Statement for FFT
ADDER^†
aDPE = –aSPE + p1
p0 = xh * yh
Multipliers
p1 = xl * yl
ALU Function Statements
aDE= aSE OP y
aSE – y
aSE & y
aDE = aDE ± aSE
Special-Purpose ALU/ACS, ADDER/ACS Function Statements for Viterbi
ALU/ACS^†
ADDER^†
aDEE = cmp0(aSEE, aDEE)
aDPE = aDPE + aSPE
aDEE = cmp0(aSEE, aDEE)
aDPE = cmp0(aSPE, aDPE)
aDE = cmp0(aSE, aDE)
aDEE = cmp1(aSE, aDEE)
aDPE = aDEE – aSE
aDEEh = cmp1(aSEEh, aSEEl)^††
aDPEh = cmp1(aSPEh, aSPEl)^††
aDE = cmp1(aSE, aDE)
aDEE = cmp2(aSE, aDEE)
aDPE = aDEE – aSE
aDE = cmp2(aSE, aDE)
aDEE = aSEE + y
aDPE = aSPE – y
aDEE = aSEE − y
aDPE = aSPE + y
aDEEh=aSEh+yh aDEEl=aSEl+yl^‡‡ aDPEh=aSEh−yh aDPEl=aSEl−yl^‡‡
aDEEh=aSEh−yh aDEEl=aSEl−yl^‡‡ aDPEh=aSEh+yh aDPEl=aSEl+yl^‡‡
Special-Purpose ALU, BMU Function Statements
ALU^†
BMU^†
aDEE = rnd(aDPE)
aDPE = aSEE >> aSPEh
aDE = aSEE >> aSPEh
aDE = abs(aDE)
aSE = aSE << ar3
aDE = aSE << ar3
aDE = aSE <<< ar3
aDEE = min(aDPE, aDEE)
aDPEh = exp(aSE)
† DAU flags are affected by the ALU or ALU/ACS operation (except for the split-mode function which does not affect the flags). If there is no ALU or
ALU/ACS operation, the DAU flags are affected by the ADDER or BMU operation.
‡ If auc0[10] (FSAT field) is set, the result of the add/subtract of the first two operands is saturated to 32 bits prior to adding/subtracting the third operand
and the final result is saturated to 32 bits.
§ If auc0[9] = 1, the least significant bit of p1 >> 15 is cleared.
†† This is a 16-bit operation. The DAU stores the result in the high half of the destination accumulator and clears the low half.
‡‡ This split-mode instruction does not affect the DAU flags. Do not set FSAT for this instruction because if FSAT is set, the entire 32 bits are saturated.
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