TMXF28155 Datasheet, PDF (68/606 Pages) Agere Systems – TMXF28155 Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
7 Microprocessor Interface and Global Control and Status Registers (continued)
Table 67. SMPR_GCR, Global Control Register (RW)
Address Bit
0x0000F 15:10
9:8
Name
—
SMPR_PMMODE[1:0]
Function
Reserved.
Performance Monitor Mode:
Reset
Default
0x0000
00 = PMRST comes from external pin.
10 = PMRST comes from external pin.
01 = PMRST comes from internal 1 second counter.
Note: Please see Table 72 and Table 73.
11 = PMRST is software controlled using the
SMPR_PMREST register bit 8 (Table 65 on
page 66).
7:5
—
Reserved.
4 SMPR_PARITY_EVEN_ODD Even or Odd Parity Indication on the Microproces-
sor Data Bus. This bit controls the parity setting and
checking on the microprocessor data bus:
0 = Even parity on microprocessor byte data/parity bus.
1 = Odd parity on microprocessor byte data/parity bus.
3
SMPR_OH_DEFLT
Overhead Default. This bit controls the filling of the
unused overhead bytes:
0 = Filling the unused overhead bits with 0.
1 = Filling the unused overhead bits with 1.
2 SMPR_FXD_STFF_DEFLT Fixed Stuff Default. This bit control the filling of the
fixed stuff bytes:
0 = Filling the fixed stuff bytes with 0.
1 = Filling the fixed stuff bytes with 1.
1
SMPR_COR_COW
Clear On Read or Clear On Write. This bit controls the
way clearing is performed on all delta and event bits in
all registers:
0 = The delta and event bit is cleared by writing a 1 to it.
Note: The clear-on-write (COW) feature does not apply
to all registers in the 28-channel framer block.
The only framer block register that has COW is
transmit FDL link register 8 (address 0x8LTD7).
All other registers in the framer block are only
clear-on-read.
1 = The delta and event bit is cleared when a micropro-
cessor read is performed on this delta and event bit.
0
SMPR_SAT_ROLLOVER Saturate or Rollover. This bit controls if error counters
hold their values or rollover when they reach their maxi-
mum values.
0 = Error counters rollover when reaching maximum val-
ues.
1 = Error counters hold their values when reaching max-
imum values.
68
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