TMXF28155 Datasheet, PDF (285/606 Pages) Agere Systems – TMXF28155 Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 389. FRM_PMLR8, Performance Monitor Link Register 8 (COR)
Address* Bit
Name
Function
0x8LP87 15:0 FRM_FBEC[15:0] Frame Bit Error Counter.
Reset Default
0x0
DS1: This register contains the 16-bit count of received
framing bit errors. Framing bit errors are not counted dur-
ing loss of frame alignment. (T1.231 section 6.1.1.2.2.)
CEPT: This register contains the 16-bit count of received
frame alignment signal errors. Optionally, bit 2 of non-FAS
frames can be counted.
Note: A FAS with errors in two or more bit positions is
only counted once.
* See Table 381 for values of L and P.
Table 390. FRM_PMLR9, Performance Monitor Link Register 9 (COR)
Address*
0x8LP88
Bit
Name
Function
Reset Default
15:0 FRM_CEC[15:0] CRC Error Counter. This register contains the 16-bit count
0x0
of received CRC errors. CRC errors are not counted during
loss of CRC multiframe alignment.
* See Table 381 for values of L and P.
Table 391. FRM_PMLR10, Performance Monitor Link Register 10 (COR)
Address*
0x8LP89
Bit
Name
Function
Reset Default
15:0 FRM_REC[15:0] Receive E-bit Counter. This register contains the 16-bit
0x0
count of received E bit = 0 events. E bit = 0 events are not
counted during loss of CEPT CRC-4 multiframe alignment.
* See Table 381 for values of L and P.
Table 392. FRM_PMLR11, Performance Monitor Link Register 11 (COR)
Address* Bit
Name
Function
Reset Default
0x8LP8A
15:0 FRM_CETE[15:0] Sa6 = 00x1 Event Counter. This register contains the
16-bit count of received Sa6 = 00x1 events. The Sa6
code is detected synchronously to the CRC-4 multiframe
and is not counted during loss of CRC-4 multiframe align-
ment. This detection is not qualified by Sa5 = 1.
0x0000
* See Table 381 for values of L and P.
Table 393. FRM_PMLR12, Performance Monitor Link Register 12 (COR)
Address*
0x8LP8B
Bit
15:0
Name
Function
FRM_CENT[15:0] Sa6 = 001x Event Counter. This register contains the
16-bit count of received Sa6 = 001x events. The Sa6 code
is detected synchronously to the CRC-4 multiframe and is
not counted during loss of CRC-4 multiframe alignment.
This detection is not qualified by Sa5 = 1.
Reset Default
0x0000
* See Table 381 for values of L and P.
Agere Systems Inc.
285