TMXF28155 Datasheet, PDF (155/606 Pages) Agere Systems – TMXF28155 Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 169. VT_REVENT_DELTA[1—28], Receive Event and Delta Per Channel (COR/COW)
Address Bit
Name
Function
Reset
Default
0x20002 15
—
Reserved.
0
—
14 VT_RX_VTREI_E[1—28] Receive REI-V Event Bit. Logic 1 indicates that
0x0
0x2001D
REI-V was received.
13 VT_RX_BIP2ERR_E[1—28] Receive BIP-2 Error Event Bit. Logic 1 indicates 0x0
that BIP-2 errors have been detected.
12 VT_RX_ESOVFL_E[1—28] Receive Elastic Store Overflow Event Bit. Logic 0x0
one indicates an elastic store overflow.
11
VT_APS_D[1—28]
ERDI-V Delta Bit. Logic 1 indicates a VTAPS
0x1
change of value.
10
VT_ERDI_D[1—28]
ERDI-V Delta Bit. Logic 1 indicates an ERDI-V
0x1
change of value.
9
VT_RDI_D[1—28]
RDI-V Delta Bit. Logic 1 indicates an RDI-V
0x1
change of value.
8
VT_RFI_D[1—28]
RFI-V Delta Bit. Logic 1 indicates an RFI-V
0x1
change of value.
7
—
Reserved.
0
6
VT_LOPS_D[1—28]
VT Loss of Phase Sync Delta Bit. Logic 1 indi-
0x1
cates a change of VTLOPS state.
5
VT_J2TIM_D[1—28]
J2 Trace Identifier Mismatch. Logic 1 indicates a 0x1
change of J2TIM state.
4
VT_PLM_D[1—28]
VT Payload Label Mismatch Delta Bit. Logic 1
0x1
indicates a change of VTPLM state.
3
VT_UNEQ_D[1—28] VT Unequip Delta Bit. Logic 1 indicates a change 0x1
of VTUNEQ state.
2
VT_SIZERR_D[1—28] VT Size Error Delta Bit. Logic 1 indicates a
0x1
change of VTSIZERR state.
1
VT_AIS_D[1—28]
AIS-V Delta Bit. Logic 1 indicates a change of
0x0
VTAIS state.
0
VT_LOP_D[1—28]
LOP-V Delta Bit. Logic 1 indicates a change of
0x1
VTLOP state.
Table 170. VT_LOPOHFAIL_EVENT, Low-Order Path Overhead Failure Event (COR/COW)
Address Bit
Name
Function
0x2001E 15:1
0
—
VT_LOPOH_FAIL_E
Reserved.
Low-Order Path Overhead Failure Event Bit. Logic 1
indicates that a failure has occurred on the LOPOH
serial access channel.
Reset
Default
0x000
0x0
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