TMXF28155 Datasheet, PDF (500/606 Pages) Agere Systems – TMXF28155 Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
21 28-Channel Framer Block Functional Description (continued)
Table 585. Transmit Signaling Link Registers 0—31 Expected Data
Signaling State Mode
16 state
4 state
2 state
Bit 6
0
0
1
Bit 5
0
1
1
Bit 4
—
—
—
Bit 3
D
—
—
Bit 2
C
—
—
Bit 1
B
B
—
Bit 0
A
A
A
The host mode can also be used to manually freeze signaling. For example, if the source is switched from receive
system to host, the existing signaling codes will be held until modified by the host or the signaling source is
switched back to the receive system. If the host mode is used to manually freeze signaling when the actual source
is the receive line interface, then signaling debounce must be enabled. Signaling debounce is enabled by setting
T_SIGDEB in the transmit signaling link register, bit 5 to 1.
If the signaling source is set to the receive system interface, the transmit signaling processor will copy exactly what
is extracted from the bus into the D, C, B, and A locations of the transmit signaling link registers 0—31 for each of
the links.
The system interface will need to be configured for ASM mode in order for the signaling to be received on the PSB
or CHI buses. ASM mode is controlled by FRM_ASM in FRM_SYSGR1, System Interface Global Register 1
(R/W), Table 347 on page 257, bit 11.
If the signaling source is set to the receive line interface, the transmit signaling processor will start extracting data
from the receive line and store valid signaling codes into the D, C, B, and A locations of the transmit signaling link
registers 0—31 for each of the links.
The transmit signaling processor will automatically determine the link type and extract the correct signaling bit posi-
tions from each link. The transmit signaling processor can simultaneously service any combination ofCEPT, DS1,
and CMI type links. The transmit signaling processor will extract robbed-bit signaling from DS1 links, common
channel signaling from CEPT links, and time slot 0 signaling from CMI links compliant with the following standards.
s ITU Rec G.704 10/98 CEPT Multiframe Signaling Structure
s T1.403 1995 Robbed-Bit Signaling
s TTC JJ-20.11 CMI Coded Interface
The transmit signaling processor can accommodate any combination of CEPT, DS1, and CMI type links when the
signaling source is set to the receive system interface.
The transmit signaling processor cannot extract signaling from the receive system and the receive line interface on
different links simultaneously.
21.14.4 Signaling Destination Selection
There are two destinations for transmit path signaling.
s Transmit Line Interface
s VT Mapper Interface
The signaling extracted from the receive system or programmed by the host will be inserted into the transmit line if
FRM_T_SIGI in FRM_TSLR32, Transmit Signaling Link Register 32 (R/W), Table 378 on page272 , bit 8, is set to
1. The transmit signaling processor will automatically detect the format of each link and insert the signaling accord-
ingly. In the case of DS1, no signaling will be inserted for those time slots whose signaling state mode is set to no-
signaling (G bit and F bit = 10). In the case of CEPT, the entiretime slot 16 multiframe is supplied from the transmit
signaling link registers 0—31.
The signaling programmed by the host or extracted from the receive system or line interface can be transported by
the VT mapper by setting FRM_T_VTSIGE in FRM_TSLR32,Transmit Signaling Link Register 32 (R/W), bit 9,
to 1.
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Agere Systems Inc.