TMXF28155 Datasheet, PDF (104/606 Pages) Agere Systems – TMXF28155 Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 107. TMUX_THS_TOH_CTL, Transmit High-speed Control Parameters (R/W) (continued)
Address Bit
Name
Function
Reset
Default
0x40035 7 TMUX_THSLREIINH Transmit Line REI Inhibit. Control bit, when set to a logic 1,
0
disables hardware insertion of line REI (B2 errors) in the outgo-
ing STM-1 (AU-4) frame M1 byte; a logic 0 enables hardware
insertion of line REI.
6 TMUX_THSLAISINS Transmit High-speed Line AIS Insertion. Control bit, when
0
set to a logic 1, causes line AIS to be inserted into the outgoing
STS-3/STM-1 (AU-4) signal; otherwise, line AIS is not sent.
5 TMUX_THSAPSINS Transmit APS Value Insert (Control). Control bit, when set to 0
a logic 1, inserts the value in TMUX_TAPSINS[12:0]
(Table 113) into the outgoing K1 and K2[7:3] bytes in the STS-
3/STM-1 (AU-4) frame; a logic 0 inserts the default value based
on SMPR_OH_DEFLT (Table 67).
4 TMUX_THSK2INS Transmit K2[2:0] Insert (Control). Control bit, when set to a
0
logic 1, inserts the value in TMUX_TK2INS[2:0] (Table 113)
into the outgoing K2 byte in the STS-3/STM-1 (AU-4) frame; a
logic 0 inserts the default value based on SMPR_OH_DEFLT.
3 TMUX_THSS1INS Transmit S1 Insert (Control). Control bit, when set to a
0
logic 1, inserts the value in TMUX_TS1INS[7:0] (Table 112)
into the outgoing S1 byte in the STS-3/STM-1 (AU-4) frame; a
logic 0 allows insertion from the TTOAC channel or a default
value.
2 TMUX_THSF1INS Transmit F1 Insert (Control). Control bit, when set to a logic
0
1, inserts the value in TMUX_TF1INS[7:0] (Table 112) into the
outgoing S1 byte in the STS-3/STM-1 (AU-4) frame; a logic 0
allows insertion from the TTOAC channel or a default value.
1 TMUX_THSZ0INS Transmit Z0-2 and Z0-3 Insert (Control). Control bit, when
0
set to a logic 1, inserts the values in TMUX_TZ02INS[7:0]
(Table 111) and TMUX_TZ03INS[7:0] (Table 111) into the out-
going Z0-2 and Z0-3 bytes in the STS-3/STM-1 (AU-4) frame; a
logic 0 inserts the default value based on SMPR_OH_DEFLT.
0 TMUX_THSJ0INS Transmit J0 Insert (Control). Control bit, when set to a logic
0
1, inserts the 16-byte sequence TMUX_TJ0DINS[16—1][7:0]
(Table 133) into the outgoing STS-3/STM-1 (AU-4) frame; a
logic 0 inserts the default value based on SMPR_OH_DEFLT.
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