TMXF28155 Datasheet, PDF (223/606 Pages) Agere Systems – TMXF28155 Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 282. M13_SEL_DS2_LB_R, Select DS2 Loopback (R/W)
Address Bit
0x10098 15:7
6:0
Name
—
M13_SEL_DS2_
LB[7:1]
Function
Reset
Default
Reserved.
0x000
If M13_SEL_DS2_LBy = 1, the DS2 Signal from Time Slot y 0x00
in the Received DS3 Signal is Looped Back into Time
Slot y of the Transmitted DS3 Signal.
Table 283. M13_RDS2_EDGE_R[1—2], Rx DS2 Edge Registers [1—2](R/W)
Address Bit
0x10099 15:7
6:0
0x1009A 15:7
6:0
Name
—
M13_RDS2_
EDGE[7:1]
—
M13_DS2ALCO_
RTM_EDGE[7:1]
Function
Reset
Default
Reserved.
0x000
A logic 1 of these Bits Means that the Received DS2 Sig-
nals are Retimed by the Rising Edge of the Associated
0x00
Clocks. A logic 0 means that the data is retimed by the falling
edge. When used in the demand clocking mode of the M23
mapping, M13_RDS2_EDGE[7:1] = 1 should be set if the
delay from the output clock to the incoming data (the maximum
should be less than 8 STS-1 clock cycles) is less than 4 STS-1
clock cycles; otherwise, M13_RDS2_EDGE[7:1] = 0 should be
used.
Reserved.
0x000
In the Demand Clocking Mode of the M23 Mapping, this
Register Provides an Extra Clock Edge Selection Capabil-
ity, in Addition to M13_RDS2_EDGE[7:1], for Retiming
0x7F
Input DS2 Data. It should normally be set to logic 1 (default).
A logic 0 is suggested only to be used with
M13_RDS2_EDGE[7:1] = 0 when necessary.
Table 284. M13_DS2_OUT_IDLE_R, DS2 Output Idle (R/W)
Address Bit
Name
Function
0x1009E 15:7
6:0
—
M13_DS2_OUT_
IDLE[7:1]
Reserved.
If M13_DS2_OUT_IDLEy = 1, the Output from DS2 Output
Selection Block y is Held Low.
Reset
Default
0x000
0x00
Table 285. M13_DS2_OUT_AIS_R, DS2 Output Alarm Indication Signal (R/W)
Address Bit
0x1009F 15:7
6:0
Name
—
M13_DS2_OUT_
AIS[7:1]
Function
Reset
Default
Reserved.
0x000
If M13_DS2_OUT_IDLEy = 0 (Table 284), a Logic 1 of this
Bit Causes DS2 AIS to be Output From the DS2 Output
Selector y; Otherwise, the DS2 Signal From Time Slot y in
the Received DS3 Signal will be Output.
0x00
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