TMXF28155 Datasheet, PDF (454/606 Pages) Agere Systems – TMXF28155 Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
19 VT/TU Mapper Functional Description (continued)
The VT mapper transmit path overhead will perform all necessary functions for the low-order path overhead as well
as the REI and RDI values from the internal SPE mapper and TMUX blocks. The following are supported:
s The interface clocks all incoming signals on the falling edge of external input LOPOHCLKIN (pin AC13).
s The first 3 bits received, following a rising edge of external input pin LOPOHVALIDIN (AB14), will define the data
type on the incoming stream. Data types are defined in Table 557, Data Type Header Definitions on page 440.
s The source of the external input LOPOHDATAIN (AC14), LOPOHVALIDIN, and LOPOHCLKIN signals is required
to hold the LOPOHVALIDIN at 0 for a minimum of eight LOPOHCLKIN cycles. The VT mapper will monitor the
incoming LOPOHVALIDIN and detect failure conditions. A failure exists if there are less than eight LOPOHCLKIN
cycles between a falling edge of LOPOHVALIDIN and the next rising edge, or if the LOPOH bit count
(LOPOH BITCNT) reaches its maximum count for the active data type and LOPOHVALIDIN does not transition
to 0.
s LOPOH failure is reported in bit VT_LOPOH_FAIL_E (Table 170). If a failure exists (VT_LOPOH_FAIL_E = 1),
the incoming data will be ignored and unless the mask bit, VT_LOPOH_FAIL_M (Table 174), is set, the LOPOH
failure will generate an interrupt.
s The VT mapper logic block will latch new REI and RDI values for the TMUX and SPE mapper during the A1 time
of the SONET/SDH frame.
The timing figures in this section are functional timing diagrams. See VT Mapper Timing on page 45 for VT mapper
interface and clock timing numbers.
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