HMC701LP6CE Datasheet, PDF (9/40 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N Synthesizer

v09.1112
HMC701LP6CE
8 GHz 16-BIT FRACTIONAL-N PLL
Reference Path ’R’ Divider
The referenced path features a 14-bit divider (rfp_div_ratio, Reg03h<13:0> Table 14) and can divide input signals
at up to 250 MHz by numbers from 1 to 16,383. The selected input reference source may be divided or bypassed
(rfp_div_select), and applied to the phase detector reference input.
Reference Path Test Features
A fractional synthesizer is a complex combination of a low phase noise analog oscillator running in close proximity with
a nearly randomly modulated delta-sigma digital modulator.
Clean spur free operation of the synthesizer requires proper board layout of power and grounds. Spurious sources
are often difficult to identify and may be related to harmonics of the digital modulation which land near the operating
frequency of the VCO, or they may arise from repeating patterns in the digital modulation itself . The loop filter and the
fractional modulator are designed to suppress these fractional spurs, but it is sometimes the case that the isolation
of the spurious products comes from layout issues. The problem is how to identify the sources of spurious products
if they occur?
The reference path of the HMC701LP6CE features some interesting test options for clocking the digital portion of the
synthesizer which may provide for a better understanding of the source of reference spurs should they occur. See
Figure 4, Table 12 and Table 29 for more register details.
For normal operation, Reg3h[15]=1. When Reg3h[15]=1, (rfp_auto_refdiv select enabled) then Reg 3 [14] & Reg 1 [2]
are ignored. If Reg 3 [13:0] is programmed to >=2, RefDiv will be enabled and the divided output will be fed to the PFD.
If Reg 3 [13:0] is programmed to 1, RefDiv will be disabled and the undivided reference signal will be fed to the PFD.
When Reg3h[15]=0 (rfp_auto_refdiv select disabled), then the state of the RefDiv is controlled by Reg 3 [14] & Reg
1 [2]. Then to enable RefDiv Reg 1 [2] = 1. To pass the divided reference signal to the PFD, Reg 3 [14]=1. If Reg
3 [14]=0, the undivided reference is passed directly to the PFD. This configuration would typically only be used for
engineering test. It allows the RefDiv to be running while the PFD is operating with the undivided reference. This
allows inspection for spurs that may be manifest from the divider running.
It is possible for example to set the synthesizer to integer mode of operation, where the digital harmonics normally
fall directly on the VCO frequency. We might chose for example to use the sine source (rfp_buf_sine_sel=1, div_
todig_en=0) to drive the reference divider. In such a case the delta sigma modulator is not normally used, however if
we wish to test the effects of the digital power supply isolation, we could input a 2^nd reference source on the square
wave input, enable its buffer (rfp_buf_sq_en=1), and enable the 2^nd crystal to clock the unused delta sigma modulator
(sqr_todig_en=1 and dsm_xref_sin_select=0). This would allow the square wave clock to be set independently of
the locked integer mode VCO, and hence measure the coupling of the digital to the sidebands of the VCO at various
frequencies. Such a test can help in identifying and debugging grounding and layout issues in the application circuit
related to the digital portion of the PCB should they occur. In general it is recommended to follow the suggested layout
closely to avoid any such problems.
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