HMC701LP6CE Datasheet, PDF (18/40 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N Synthesizer

v09.1112
HMC701LP6CE
8 GHz 16-BIT FRACTIONAL-N PLL
Cycle Slip Prevention (CSP)
When changing frequencies the VCO is not yet locked to the reference and the phase difference at the PFD varies
rapidly over a range much greater than ±2π radians. Since the gain of the PFD varies linearly with phase up to ±2π,
the gain of conventional PFDs will cycle from high gain, when the phase difference approaches a multiple of 2π, to
low gain, when the phase difference is slightly larger than a multiple of 0 radians. This phenomena is known as cycle
slipping. Cycle slipping causes the pull-in rate during the locking phase to vary cyclically as shown in the red curve in
Figure 13. Cycle slipping increases the time to lock to a value far greater than that predicted by normal small signal
Laplace analysis.
The HMC701LP6CE PFD features Cycle Slip Prevention (CSP), an ability to virtually eliminate cycle slipping during
acquisition. When enabled, the CSP feature essentially holds the PFD gain at maximum until such time as the
frequency difference is near zero. CSP allows significantly faster lock times as shown in Figure 13. The use of the
CSP feature is enabled with pfds_rstb (Reg01<15> Table 12). The CSP feature may be optimized for a given set
of PLL dynamics by adjusting the PFD sensitivity to cycle slipping. This is achieved by adjusting pfds_sat_deltaN
(Reg1C<3:0> Table 38).
CSP will cause the VCO N divider to momentarily divide by a higher or lower N value in order to pull the divided VCO
phase back towards the reference edge. The maximum recommended VCO N divider deviation is no more than 20%
of the target N value. For example, if N=50 for the target frequency, then the CSP Magnitude should be 10 or less so
Register 1Ch Bits [3:0] would be programmed to Ah.
In situations where the target N value is low, for example 36 the CSP behavior will be compromised because the
minimum VCO divide value is 32
Figure 13. Cycle Slip Prevention (CSP)
Charge Pump Gain
A simplified diagram of the charge pump is shown in Figure 14. Charge pump up and down gains are set by cp_
UPcurrent_sel and cp_DNcurrent_sel respectively (Reg07 Table 18). Normally the registers are set to the same
value. Each of the UP and DN charge pumps consist of 5-bit charge pumps with lsb of 125 µA. The current gain of the
pump, in Amps/radian, is equal to the gain setting of this register divided by 2π.
For example if both cp_UPcurrent_sel and cp_DNcurrent_sel are set to ’01000’ the output current of each pump will
be 1mA and the gain Kp = 1mA/2π radians, or 159 uA/rad.
Charge Pump Gain Trim
In most applications Gain Trim is not used. However it is available for special applications.
Each of the UP and DN pumps may be trimmed separately to more precise values to improve current source matching
of the UP and DN values, or to allow finer control of pump gain.
The pump trim controls are 3-bits, binary weighted for UP and DN, in cp_UPtrim_sel and cp_DNtrim_sel respectively
(Reg 08h Table 19). LSB weight is 14.7 uA, x000 = 0 trim, x001 = 14.7 ua added trim, x111 = 100uA.
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