HMC701LP6CE Datasheet, PDF (27/40 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N Synthesizer

v09.1112
HMC701LP6CE
8 GHz 16-BIT FRACTIONAL-N PLL
A typical WRITE cycle is shown in Figure 19.
a. The Master (host) both asserts SEN (Serial Port Enable) and clears SDI to indicate a WRITE
cycle, followed by a rising edge of SCLK.
b. The slave (synthesizer) reads SDI on the 1st rising edge of SCLK after SEN. SDI low initiates
the WRITE cycle (/WR)
c. Host places the six address bits on the next six falling edges of SCLK, MSB first.
d. Slave registers the address bits in the next six rising edges of SCLK (2-7).
e. Host places the 24 data bits on the next 24 falling edges of SCK, MSB first .
f. Slave registers the data bits on the next 24 rising edges of SCK (8-31).
g. SEN is de-asserted on or after the 32nd falling edge of SCLK.
h. The 32^nd rising edge of SCLK completes the cycle
Figure 19. Serial Port Timing Diagram - WRITE
Main Serial Port READ Operation
AVDD = DVDD = 3V ±10%, AGND = DGND = 0V
Table 5. Timing Characteristics
Parameter
Conditions
t₁
SEN to SCLK setup time
t₂
SDI to SCLK setup time
t₃
SCLK to SDI hold time
t₄
SCLK high duration
t₅
SCLK low duration
t₆
SEN High duration
t₇
SEN Low duration
t₈
SCLK to SDO delay
t₉
Recovery Time
Min.
8
10
10
8
8
640
20
Typ.
Max
8ns+0.2ns/pF
10
Units
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
The synthesizer uses the multi-purpose pin, LD_SDO, for both Lock Detect and Serial Data Out (SDO) functions. The
registers lkd_to_sdo_automux_en (Reg1A<12>) and lkd_to_sdo_always (Reg1A<13> Table 36) determine how the
Data Output pin is muxed with the Lock Detect function. If both of the registers are cleared, then the pin is exclusively
SDO. If automux is enabled, the pin switches to SDO when the RD function is sensed on the 1st rising edge of SCLK.
If lkd_to_sdo_always is set, then the pin LD_SDO is dedicated for Lock Detect only, and it is not possible to read from
the synthesizer.
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