HMC701LP6CE Datasheet, PDF (30/40 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N Synthesizer

v09.1112
HMC701LP6CE
8 GHz 16-BIT FRACTIONAL-N PLL
Table 14. Reg 03h Reference Path Register
Bit
Type
Name
Default
13:0
R/W
rfp_div_ratio
also referred to as ‘R’
1
14
R/W rfp_div_select
0
15
R/W rfp_auto_refdiv_sel_en
1
16
R/W rfp_buf_sin_sel
0
Description
Divides the crystal input by this number ‘R’ if
rfp_div_en=1 and rfp_div_select = 1
rfp_div_ratio = 0 not allowed
2<=div_ratio<=2^14
see Figure 4
1 = reference divider enabled
0 = bypass ref divider
see Figure 4
1 = auto ref divider enable or bypass is automatic
if rfp_div_ratio = 1, bypass divider
if rfp_div_bypass ~=1 use divider
see Figure 4
Selects sine wave reference for normal operation
see Figure 4
Table 15. Reg 04h Prescaler Duty Cycle Register
Bit
Type
Name
Default
0
R/W vcop_dutycycmode
0
Description
Extends the low time from 15 to 47 VCO cycles
for large divide ratios. Program 0
Table 16. Reg 05h Phase Freq Detector Register (pfd)
Bit
Type
Name
Default
Description
0
R/W pfd_phase_sel
Inverts PFD Polarity
0 = Passive Filter +ve slope VCO
0
1 = Passive Filter -ve slope VCO
1 = Active inverting filter, +ve slope VCO
0 = Active inverting filter, -ve slope VCO
1
R/W pfd_upout_en
1
Allows masking of the up outputs between PFD
and CP
2
R/W pfd_dnout_en
1
Allows masking of the dn outputs between PFD
and CP
Table 17. Reg 06h Phase Freq Detector Delay Register
Bit
Type
Name
Default
Description
2:0
R/W pfd_del_sel
2h
Delay line setpoint to PFD Program 001
Table 18. Reg 07h Charge Pump UP/DN Control Register
Bit
Type
Name
Default
Description
4:0
R/W cp_UPcurrent_sel
10h
Sets Charge-Pump Up gain, 125uA lsb, binary,
4mA max. Program as needed
9:5
R/W cp_DNcurrent_sel
10h
Sets Charge-Pump Dn gain, 125uA lsb, binary,
4mA max. Program as needed
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