HMC701LP6CE Datasheet, PDF (28/40 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N Synthesizer

v09.1112
HMC701LP6CE
8 GHz 16-BIT FRACTIONAL-N PLL
A typical READ cycle is shown in Figure 20.
a. The Master (host) asserts both SEN (Serial Port Enable) and SDI to indicate a READ
cycle, followed by a rising edge SCLK
b. The slave (synthesizer) reads SDI on the 1st rising edge of SCLK after SEN. SDI high initiates
the READ cycle (RD)
c. Host places the six address bits on the next six falling edges of SCLK, MSB first.
d. Slave registers the address bits on the next six rising edges of SCLK (2-7).
e. Slave places the 24 data bits on the next 24 rising edges of SCK (8-31), MSB first .
f. Host registers the data bits on the next 24 falling edges of SCK (8-31).
g. SEN is de-asserted on or after the 32nd falling edge of SCLK.
h. The 32nd falling edge of SCLK completes the cycle
Figure 20. Serial Port Timing Diagram - READ
REGISTER MAP
Reg 00h Chip ID (Read Only) Register
Bit
Type
Name
Width
[23:0]
RO
Chip ID
24
Default
581502h Chip ID
Description
Table 11. Reg 00h Strobe (Write Only) Register
Bit
Type
Name
Width
Default
0
STR global_swrst_regs
1
0
1
STR global_swrst_dig
1
0
2
STR mcnt_resynch
1
0
3
STR tsens_spi_strobe
1
0
Description
Strobe to soft reset the SPI registers
Strobe to soft reset the rest of digital
Reserved
Strobe to clock the temp measurement on
demand
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