HMC701LP6CE Datasheet, PDF (25/40 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N Synthesizer

v09.1112
HMC701LP6CE
8 GHz 16-BIT FRACTIONAL-N PLL
Figure 17. Single Step Ramp Mode
The user should be aware that the synthesized ramp is subject to normal phase locked loop dynamics. If the loop
bandwidth in use is much wider than the rate of the steps then the locking will be very fast and the ramp will have a
staircase shape. If the update rate is higher than the loop bandwidth, as is normally the case, then the loop will not
fully settle before a new frequency step is received. Hence the swept output will have a small lag and will sweep in a
near continuous fashion.
MAIN SERIAL PORT
The HMC701LP6CE features a four wire serial port for simple communication with the host controller. Register types
may be Read Only, Write Only, Read/Write or Strobe, as described in the registers descriptions.
Typical main serial port operation can be run with SCLK at speeds up to 50 MHz. Serial port registers are described
in the section REGISTER MAP.
LD_SDO Pin Operation
Configuration of the LD_SDO pin requires manipulation of both Reg2h[1:0] and Reg1Ah[13:12], as follows:
Serial data output (SDO) when a serial read occurs and high impedance at all other times:
Reg2h[1:0] = 0x (x=don’t care)
Reg1Ah[13:12] = 0x (x=don’t care)
Serial data output (SDO) when a serial read occurs and LD status at all other times (LD_SDO pin automatically mux’ed
between LD and SDO):
Reg2h[1:0] = 11
Reg1Ah[13:12] = 01
LD status always:
Reg2h[1:0] = 11
Reg1Ah[13:12] = 1x
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