EX128-PTQG100 Datasheet, PDF (29/49 Pages) Actel Corporation – eX Family FPGAs

eX Family FPGAs
Table 1-20 • eX Family Timing Characteristics
(Worst-Case Commercial Conditions V_CCA = 2.3 V, T_J = 70°C)
‘–P’ Speed
Parameter Description
2.5 V LVCMOS Output Module Timing¹ (V_CCI = 2.3 V)
t_DLH
Data-to-Pad LOW to HIGH
t_DHL
Data-to-Pad HIGH to LOW
t_DHLS
Data-to-Pad HIGH to LOW—Low Slew
t_ENZL
Enable-to-Pad, Z to L
t_ENZLS
Enable-to-Pad Z to L—Low Slew
t_ENZH
Enable-to-Pad, Z to H
t_ENLZ
Enable-to-Pad, L to Z
t_ENHZ
Enable-to-Pad, H to Z
d_TLH
Delta Delay vs. Load LOW to HIGH
d_THL
Delta Delay vs. Load HIGH to LOW
d_THLS
Delta Delay vs. Load HIGH to LOW—Low Slew
3.3 V LVTTL Output Module Timing¹ (V_CCI = 3.0 V)
t_DLH
Data-to-Pad LOW to HIGH
t_DHL
Data-to-Pad HIGH to LOW
t_DHLS
Data-to-Pad HIGH to LOW—Low Slew
t_ENZL
Enable-to-Pad, Z to L
t_ENZLS
Enable-to-Pad Z to L—Low Slew
t_ENZH
Enable-to-Pad, Z to H
t_ENLZ
Enable-to-Pad, L to Z
t_ENHZ
Enable-to-Pad, H to Z
d_TLH
Delta Delay vs. Load LOW to HIGH
d_THL
Delta Delay vs. Load HIGH to LOW
d_THLS
Delta Delay vs. Load HIGH to LOW—Low Slew
5.0 V TTL Output Module Timing^* (V_CCI = 4.75 V)
t_DLH
Data-to-Pad LOW to HIGH
t_DHL
Data-to-Pad HIGH to LOW
t_DHLS
Data-to-Pad HIGH to LOW—Low Slew
t_ENZL
Enable-to-Pad, Z to L
t_ENZLS
Enable-to-Pad Z to L—Low Slew
t_ENZH
Enable-to-Pad, Z to H
t_ENLZ
Enable-to-Pad, L to Z
Note: *Delays based on 35 pF loading.
Min.
Max.
3.3
3.5
11.6
2.5
11.8
3.4
2.1
2.4
0.034
0.016
0.05
2.8
2.7
9.7
2.2
9.7
2.8
2.8
2.6
0.02
0.016
0.05
2.0
2.6
6.8
1.9
6.8
2.1
3.3
‘Std’ Speed
Min. Max.
4.7
5.0
16.6
3.6
16.9
4.9
3.0
5.67
0.046
0.022
0.072
4.0
3.9
13.9
3.2
13.9
4.0
4.0
3.8
0.03
0.022
0.072
2.9
3.7
9.7
2.7
9.8
3.0
4.8
‘–F’ Speed
Min. Max.
6.6
7.0
23.2
5.1
23.7
6.9
4.2
7.94
0.066
0.05
0.1
5.6
5.4
19.5
4.4
19.6
5.6
5.6
5.3
0.046
0.05
0.1
4.0
5.2
13.6
3.8
13.7
4.1
6.6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
v4.3
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