EX128-PTQG100 Datasheet, PDF (23/49 Pages) Actel Corporation – eX Family FPGAs

Output Buffer Delays
eX Family FPGAs
E
D
TRIBUFF
PAD To AC test loads (shownbelow)
V_CC
In 50% 50% GND
VOH
Out
1.5 V
1.5 V
VOL _tDLH
tDHL
Table 1-13 • Output Buffer Delays
VCC
En ^{50% 50%}
GND
VCC
Out
1.5 V
10%
tENZL ^VOL tENLZ
AC Test Loads
Load 1
(used to measure
propagation delay)
To the output
under test
35 pF
Load 2
(Used to measure enable delays)
V_CC ^GND
To the output
under test
R
R
to
to
GV^CN^CDfofrotrPtZPLHZ
R = 1 kΩ
35 pF
V_CC
En 50% 50%
GND
Out
GND _tENZH
VOH
1.5 V
90%
tENHZ
Load 3
(Used to measure disable delays)
VCC ^GND
To the output
under test
R
R
to
to
GV^CN^CDfofrotrPtLPZHZ
R = 1 kΩ
5 pF
Figure 1-15 • AC Test Loads
v4.3
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