EX128-PTQG100 Datasheet, PDF (22/49 Pages) Actel Corporation – eX Family FPGAs

eX Family FPGAs
eX Timing Model
Input Delays
I/O Module
t_INYH= 0.7 ns
t_IRD1 = 0.3 ns
t_IRD2 = 0.4 ns
Internal Delays
Combinatorial
Cell
Predicted
Routing
Delays
Output Delays
I/O Module
Routed
Clock
Hard-Wired
Clock
tt^SHUDD==00.0.5nnss
t_PD = 0.7 ns
Register
Cell
ttt_RRRDDD841
=
=
=
0.3
0.7
1.2
ns
ns
ns
t_DHL = 2.6 ns
I/O Module
DQ
t_RD1 = 0.3 ns
t_ENZL= 1.9 ns
t_DHL = 2.6 ns
t_RCKH= 1.3 ns
(100% Load)
t_RCO= 0.6 ns
I/O Module
t_INYH= 1.3 ns
t_IRD1 = 0.3 ns
t
t
SUD ^{= 0.5 ns}
HD ^{= 0.0 ns}
Register
Cell
DQ
t_RD1 = 0.3 ns
I/O Module
t_ENZL= 1.9 ns
t_DHL = 2.6 ns
t_HCKH= 1.1 ns
t_RCO= 0.6 ns
Note: Values shown for eX128–P, worst-case commercial conditions (5.0V, 35pF Pad Load).
Figure 1-14 • eX Timing Model
Hardwired Clock
External Setup = t_INYH + t_IRD1 + t_SUD – t_HCKH
= 0.7 + 0.3 + 0.5 – 1.1 = 0.4 ns
Clock-to-Out (Pad-to-Pad), typical
= t_HCKH + t_RCO + t_RD1 + t_DHL
= 1.1 + 0.6 + 0.3 + 2.6 = 4.6 ns
Routed Clock
External Setup = t_INYH + t_IRD2 + t_SUD – t_RCKH
= 0.7 + 0.4 + 0.5 – 1.3= 0.3 ns
Clock-to-Out (Pad-to-Pad), typical
= t_RCKH + t_RCO + t_RD1 + t_DHL
= 1.3+ 0.6 + 0.3 + 2.6 = 4.8 ns
1-18
v4.3