EX128-PTQG100 Datasheet, PDF (15/49 Pages) Actel Corporation – eX Family FPGAs

eX Family FPGAs
Explorer II's noninvasive method does not alter timing or
loading effects, thus shortening the debug cycle.
Silicon Explorer II does not require re-layout or
additional MUXes to bring signals out to an external pin,
which is necessary when using programmable logic
devices from other suppliers.
Silicon Explorer II samples data at 100 MHz
(asynchronous) or 66 MHz (synchronous). Silicon Explorer
II attaches to a PC's standard COM port, turning the PC
into a fully functional 18-channel logic analyzer. Silicon
Explorer II allows designers to complete the design
verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation. Figure 1-13 illustrates the
interconnection between Silicon Explorer II and the eX
device to perform in-circuit verification.
Design Considerations
The TDI, TCK, TDO, PRA, and PRB pins should not be used
as input or bidirectional ports. Since these pins are active
during probing, critical signals input through these pins
are not available while probing. In addition, the Security
Fuse should not be programmed because doing so
disables the probe circuitry. It is recommended to use a
series 70Ω termination resistor on every probe connector
(TDI, TCK, TMS, TDO, PRA, PRB). The 70Ω series
termination is used to prevent data transmission
corruption during probing and reading back the
checksum.
Table 1-8 • Device Configuration Options for Probe Capability (TRST pin reserved)
JTAG Mode
TRST¹
Security Fuse Programmed
PRA, PRB²
Dedicated
LOW
No
User I/O³
Flexible
LOW
No
User I/O³
TDI, TCK, TDO²
Probing Unavailable
User I/O³
Dedicated
HIGH
No
Probe Circuit Outputs
Probe Circuit Inputs
Flexible
HIGH
No
Probe Circuit Outputs
Probe Circuit Inputs
–
–
Yes
Probe Circuit Secured
Probe Circuit Secured
Notes:
1. If TRST pin is not reserved, the device behaves according to TRST = HIGH in the table.
2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
signals will not pass through these pins and may cause contention.
3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by
Actel’s Designer software.
16 Pin
Connection
TDI
TCK
Serial
Connection
Silicon Explorer II
TMS
TDO
PRA
PRB
22 Pin
Connection
Additional 16 Channels
(Logic Analyzer)
Figure 1-13 • Silicon Explorer II Probe Setup
eX FPGAs
v4.3
1-11