EX128-PTQG100 Datasheet, PDF (10/49 Pages) Actel Corporation – eX Family FPGAs

eX Family FPGAs
Hot Swapping
eX I/Os are configured to be hot-swappable. During
power-up/down (or partial up/down), all I/Os are
tristated, provided V_CCA ramps up within a diode drop of
V_CCI. V_CCA and V_CCI do not have to be stable during
power-up/down, and they do not require a specific
power-up or power-down sequence in order to avoid
damage to the eX devices. In addition, all outputs can be
programmed to have a weak resistor pull-up or pull-
down for output tristate at power-up. After the eX
device is plugged into an electrically active system, the
device will not degrade the reliability of or cause
damage to the host system. The device's output pins are
driven to a high impedance state until normal chip
operating conditions are reached. Please see the
application note, Actel SX-A and RT54SX-S Devices in
Hot-Swap and Cold-Sparing Applications, which also
applies to the eX devices, for more information on hot
swapping.
Power Requirements
Power consumption is extremely low for the eX family
due to the low capacitance of the antifuse interconnects.
The antifuse architecture does not require active circuitry
to hold a charge (as do SRAM or EPROM), making it the
lowest-power FPGA architecture available today.
Low Power Mode
The eX family has been designed with a Low Power
Mode. This feature, activated with setting the special LP
pin to HIGH for a period longer than 800 ns, is
particularly useful for battery-operated systems where
battery life is a primary concern. In this mode, the core of
the device is turned off and the device consumes minimal
power with low standby current. In addition, all input
buffers are turned off, and all outputs and bidirectional
buffers are tristated when the device enters this mode.
Since the core of the device is turned off, the states of
the registers are lost. The device must be re-initialized
when returning to normal operating mode. I/Os can be
driven during LP mode. For details, refer to the Design
for Low Power in Actel Antifuse FPGAs application note
under the section Using the LP Mode Pin on eX Devices.
Clock pins should be driven either HIGH or LOW and
should not float; otherwise, they will draw current and
burn power. The device must be re-initialized when
exiting LP mode. To exit the LP mode, the LP pin must be
driven LOW for over 200µs to allow for the charge
pumps to power-up and device initialization can begin.
Table 1-3 illustrates the standby current of eX devices in
LP mode.
Table 1-3 • Standby Power of eX Devices in LP Mode
Typical Conditions, V_CCA, V_CCI = 2.5 V, T_J = 25° C
Product Low Power Standby Current
Units
eX64
100
µA
eX128
111
µA
eX256
134
µA
1-6
v4.3