EX128-PTQG100 Datasheet, PDF (24/49 Pages) Actel Corporation – eX Family FPGAs

eX Family FPGAs
Input Buffer Delays
PAD
Y
INBUF
In
Out
GND
3V
1.5 V 1.5 V
0V
VCC
50%
50%
t_INY
t_INY
Table 1-14 • Input Buffer Delays
Cell Timing Characteristics
C-Cell Delays
S
AY
B
S, A or B
Out
GND
Out
VCC
50% 50%
VCC
50%
GND
50%
tPD
50%
tPD
tPD
GND
tPD
VCC
50%
Table 1-15 • C-Cell Delays
D
CLK
Q
CLR
PRESET
Figure 1-16 • Flip-Flops
t _SUD
D _PRESET Q
CLK _CLR
(Positive edge triggered)
t_HD
t
t
HPWH^,
RPWH
t_RCO
t_{H P}
t_HPWL, t_RPWL
t_CLR
t_WASYN
t_PRESET
1-20
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