EX128-PTQG100 Datasheet, PDF (14/49 Pages) Actel Corporation – eX Family FPGAs

eX Family FPGAs
JTAG Instructions
Table 1-6 lists the supported instructions with the
corresponding IR codes for eX devices.
Table 1-6 • JTAG Instruction Code
Instructions (IR4: IR0)
Binary Code
EXTEST
00000
SAMPLE / PRELOAD
00001
INTEST
00010
USERCODE
00011
IDCODE
00100
HIGHZ
01110
CLAMP
01111
Diagnostic
10000
BYPASS
11111
Reserved
All others
Table 1-7 lists the codes returned after executing the
IDCODE instruction for eX devices. Note that bit 0 is
always "1." Bits 11-1 are always "02F", which is Actel's
manufacturer code.
Table 1-7 • IDCODE for eX Devices
Device
Revision Bits 31-28 Bits 27-12
eX64
0
8
40B2, 42B2
eX128
0
9
40B0, 42B0
eX256
0
9
40B5, 42B5
eX64
1
A
40B2, 42B2
eX128
1
B
40B0, 42B0
eX256
1
B
40B5, 42B5
Programming
Device programming is supported through Silicon
Sculptor series of programmers. In particular, Silicon
Sculptor II is a compact, robust, single-site and multi-site
device programmer for the PC.
With standalone software, Silicon Sculptor II allows
concurrent programming of multiple units from the
same PC, ensuring the fastest programming times
possible. Each fuse is subsequently verified by Silicon
Sculptor II to insure correct programming. In addition,
integrity tests ensure that no extra fuses are
programmed. Silicon Sculptor II also provides extensive
hardware self-testing capability.
The procedure for programming an eX device using
Silicon Sculptor II is as follows:
1. Load the .AFM file
2. Select the device to be programmed
3. Begin programming
When the design is ready to go to production, Actel
offers device volume-programming services either
through distribution partners or via in-house
programming from the factory.
For more details on programming eX devices, please
refer to the Programming Antifuse Devices application
note and the Silicon Sculptor II User's Guide.
Probing Capabilities
eX devices provide internal probing capability that is
accessed with the JTAG pins. The Silicon Explorer II
Diagnostic hardware is used to control the TDI, TCK, TMS
and TDO pins to select the desired nets for debugging.
The user simply assigns the selected internal nets in the
Silicon Explorer II software to the PRA/PRB output pins
for observation. Probing functionality is activated when
the BST pins are in JTAG mode and the TRST pin is driven
HIGH or left floating. If the TRST pin is held LOW, the
TAP controller will remain in the Test-Logic-Reset state so
no probing can be performed. The Silicon Explorer II
automatically places the device into JTAG mode, but the
user must drive the TRST pin HIGH or allow the internal
pull-up resistor to pull TRST HIGH.
When you select the "Reserve Probe Pin" box as shown
in Figure 1-12 on page 1-9, the layout tool reserves the
PRA and PRB pins as dedicated outputs for probing. This
"reserve" option is merely a guideline. If the Layout tool
requires that the PRA and PRB pins be user I/Os to
achieve successful layout, the tool will use these pins for
user I/Os. If you assign user I/Os to the PRA and PRB pins
and select the "Reserve Probe Pin" option, Designer
Layout will override the "Reserve Probe Pin" option and
place your user I/Os on those pins.
To allow for probing capabilities, the security fuse must
not be programmed. Programming the security fuse will
disable the probe circuitry. Table 1-8 on page 1-11
summarizes the possible device configurations for
probing once the device leaves the "Test-Logic-Reset"
JTAG state.
Silicon Explorer II Probe
Silicon Explorer II is an integrated hardware and
software solution that, in conjunction with Actel’s
Designer software tools, allow users to examine any of
the internal nets of the device while it is operating in a
prototype or a production system. The user can probe
into an eX device via the PRA and PRB pins without
changing the placement and routing of the design and
without using any additional resources. Silicon
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