EX128-PTQG100 Datasheet, PDF (26/49 Pages) Actel Corporation – eX Family FPGAs

eX Family FPGAs
eX Family Timing Characteristics
Table 1-17 • eX Family Timing Characteristics
(Worst-Case Commercial Conditions, V_CCA = 2.3 V_, T_J = 70°C)
‘–P’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Units
C-Cell Propagation Delays¹
t_PD
Internal Array Module
Predicted Routing Delays²
0.7
1.0
1.4
ns
t_DC
FO=1 Routing Delay, DirectConnect
t_FC
FO=1 Routing Delay, FastConnect
t_RD1
FO=1 Routing Delay
t_RD2
FO=2 Routing Delay
t_RD3
FO=3 Routing Delay
t_RD4
FO=4 Routing Delay
t_RD8
FO=8 Routing Delay
t_RD12
FO=12 Routing Delay
R-Cell Timing
0.1
0.1
0.2
ns
0.3
0.5
0.7
ns
0.3
0.5
0.7
ns
0.4
0.6
0.8
ns
0.5
0.8
1.1
ns
0.7
1.0
1.3
ns
1.2
1.7
2.4
ns
1.7
2.5
3.5
ns
t_RCO
Sequential Clock-to-Q
t_CLR
Asynchronous Clear-to-Q
t_PRESET
Asynchronous Preset-to-Q
t_SUD
Flip-Flop Data Input Set-Up
t_HD
Flip-Flop Data Input Hold
t_WASYN
Asynchronous Pulse Width
t_RECASYN
Asynchronous Recovery Time
t_HASYN
Asynchronous Hold Time
2.5 V Input Module Propagation Delays
0.6
0.9
1.3
ns
0.6
0.8
1.2
ns
0.7
0.9
1.3
ns
0.5
0.7
1.0
ns
0.0
0.0
0.0
ns
1.3
1.9
2.6
ns
0.3
0.5
0.7
ns
0.3
0.5
0.7
ns
t_INYH
Input Data Pad-to-Y HIGH
t_INYL
Input Data Pad-to-Y LOW
3.3 V Input Module Propagation Delays
0.6
0.9
1.3
ns
0.8
1.1
1.5
ns
t_INYH
Input Data Pad-to-Y HIGH
t_INYL
Input Data Pad-to-Y LOW
5.0 V Input Module Propagation Delays
0.7
1.0
1.4
ns
0.9
1.3
1.8
ns
t_INYH
Input Data Pad-to-Y HIGH
t_INYL
Input Data Pad-to-Y LOW
Input Module Predicted Routing Delays²
0.7
1.0
1.4
ns
0.9
1.3
1.8
ns
t_IRD1
t_IRD2
t_IRD3
t_IRD4
t_IRD8
t_IRD12
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
0.3
0.4
0.5
ns
0.4
0.6
0.8
ns
0.5
0.8
1.1
ns
0.7
1.0
1.3
ns
1.2
1.7
2.4
ns
1.7
2.5
3.5
ns
1. For dual-module macros, use t_PD + t_RD1 + t_PDn, t_RCO + t_RD1 + t_PDn or t_PD1 + t_RD1 + t_SUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
1-22
v4.3