EX128-PTQG100 Datasheet, PDF (27/49 Pages) Actel Corporation – eX Family FPGAs

eX Family FPGAs
Table 1-18 • eX Family Timing Characteristics
(Worst-Case Commercial Conditions V_CCA = 2.3 V, V_CCI = 4.75 V, T_J = 70°C)
‘–P’ Speed
‘Std’ Speed
Parameter Description
Min. Max. Min. Max.
Dedicated (Hard-Wired) Array Clock Networks
t_HCKH
Input LOW to HIGH
(Pad to R-Cell Input)
1.1
1.6
t_HCKL
Input HIGH to LOW
(Pad to R-Cell Input)
1.1
1.6
t_HPWH
Minimum Pulse Width HIGH
t_HPWL
Minimum Pulse Width LOW
t_HCKSW
Maximum Skew
t_HP
Minimum Period
f_HMAX
Maximum Frequency
Routed Array Clock Networks
1.4
2.0
1.4
2.0
<0.1
<0.1
2.8
4.0
357
250
t_RCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) MAX.
1.1
1.6
t_RCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) MAX.
1.0
1.4
t_RCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
t_RCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
t_RCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) MAX.
1.3
1.9
t_RCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) MAX.
1.3
1.9
t_RPWH
Min. Pulse Width HIGH
1.5
2.1
t_RPWL
Min. Pulse Width LOW
1.5
2.1
t_RCKSW*
Maximum Skew (Light Load)
0.2
0.3
t_RCKSW*
Maximum Skew (50% Load)
0.1
0.2
t_RCKSW*
Maximum Skew (100% Load)
0.1
0.1
Note: *Clock skew improves as the clock network becomes more heavily loaded.
‘–F’ Speed
Min. Max. Units
2.3
ns
2.3
ns
2.8
ns
2.8
ns
<0.1
ns
5.6
ns
178 MHz
2.2
ns
2.0
ns
2.4
ns
2.4
ns
2.6
ns
2.6
ns
3.0
ns
3.0
ns
0.4
ns
0.3
ns
0.2
ns
v4.3
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