WCSS0418V1P Datasheet, PDF (7/17 Pages) Weida Semiconductor, Inc. – 256K x 18 Synchronous-Pipelined Cache RAM

WCSS0418V1P
Write Cycle Description^{[4, 5, 6]}
Function
Read
Read
Write Byte 0 - DQ_[7:0]
Write Byte 1 - DQ_[15:8]
Write Bytes 1, 0
Write Byte 2 - DQ_[23:16]
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 - DQ_[31:24]
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
Write All Bytes
GW
BWE
BW₃
BW₂
BW₁
BW₀
1
1
X
X
X
X
1
0
1
1
1
1
1
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
0
1
0
0
1
1
1
1
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
X
X
X
X
X
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage on V_DD Relative to GND.........−0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State^[7] ....................................... −0.5V to V_DD + 0.5V
DC Input Voltage^[7].................................... −0.5V to V_DD + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Ambient
Range Temperature^[8]
Com’l
0°C to +70°C
Industrial –40°C to +85°C
V_DD
3.3V
−5%/+10%
V_DDQ
2.5V −5%
3.3V +10%
Notes:
4. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW.
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW_[1:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ_[15:0];DP_[1:0] = High-Z when OE is
inactive or when the device is deselected, and DQ_[15:0];DP_[1:0] = data when OE is active.
7. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.
8. T_A is the case temperature.
Document #: 38-05247
Page 7 of 17