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| WCSS0418V1P Datasheet, PDF (11/17 Pages) Weida Semiconductor, Inc. – 256K x 18 Synchronous-Pipelined Cache RAM | |||
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WCSS0418V1P
Switching Waveforms (continued)
Read Cycle Timing[14, 16]
CLK
Single Read
tCYC
tCH
Burst Read
Pipelined Read
Unselected
tADS
tADH
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC
ADV
tADVS
tADH
tAS
ADD
RD1
tADVH
RD2
tAH
GW
tWS
tWH
WE
CE1
tCES tCEH
ADSC initiated read
Suspend Burst
RD3
tWS
tWH
CE1 masks ADSP
CE2
tCES
CE3
tCES
OE
Data Out
tCEH
tCEH
tEOV
tOEHZ
tCO
11aa
tCLZ
tDOH
2a
2b
2c 2c
= DONâT CARE
= UNDEFINED
Unselected with CE2
2d
3a
tCHZ
Note:
16. RDx stands for Read Data from Address X.
Document #: 38-05247
Page 11 of 17
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