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| WCSS0418V1P Datasheet, PDF (12/17 Pages) Weida Semiconductor, Inc. – 256K x 18 Synchronous-Pipelined Cache RAM | |||
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Switching Waveforms (continued)
Read/Write Cycle Timing[14, 15, 16, 17]
WCSS0418V1P
CLK
tADS
ADSP
ADSC
ADV
Single Read
tCYC
Single Write
tCH
tADH
tADS
tADVS
tCL
tADH
Burst Read
Unselected
Pipelined Read
ADSP ignored with CE1 inactive
tAS
ADD
RD1
tADVH
WD2
tAH
GW
tWS
tWH
WE
tCES
CE1
tCEH
RD3
tWS
tWH
CE1 masks ADSP
CE2
tCES
CE3
tCES
OE
tCEH
tCEH
tEOV
tEOHZ
Data In/Out
tEOLZ
tCO
1O1aaut
2a
In
See Note 17
tDS tDH
2a
3a
3b
Out Out
Out
= DONâT CARE = UNDEFINED
Note:
17. Data bus is driven by SRAM, but data is not guaranteed.
tDOH
3c
3d
Out
Out
tCHZ
Document #: 38-05247
Page 12 of 17
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