WCSS0418V1P Datasheet, PDF (6/17 Pages) Weida Semiconductor, Inc. – 256K x 18 Synchronous-Pipelined Cache RAM

WCSS0418V1P
Cycle Descriptions^{[1, 2, 3]}
Next Cycle Add. Used ZZ
Unselected
None
L
CE₃ CE₂ CE₁ ADSP ADSC ADV OE
X
X
1
X
0
X
X
Unselected
None
L
1
X
0
0
X
X
X
Unselected
None
L
X
0
0
0
X
X
X
Unselected
None
L
1
X
0
1
0
X
X
Unselected
None
L
X
0
0
1
0
X
X
Begin Read
External
L
0
1
0
0
X
X
X
Begin Read
External
L
0
1
0
1
0
X
X
Continue Read Next
L
X
X
X
1
1
0
1
Continue Read Next
L
X
X
X
1
1
0
0
Continue Read Next
L
X
X
1
X
1
0
1
Continue Read Next
L
X
X
1
X
1
0
0
Suspend Read Current
L
X
X
X
1
1
1
1
Suspend Read Current
L
X
X
X
1
1
1
0
Suspend Read Current
L
X
X
1
X
1
1
1
Suspend Read Current
L
X
X
1
X
1
1
0
Begin Write
Current
L
X
X
X
1
1
1
X
Begin Write
Current
L
X
X
1
X
1
1
X
Begin Write
External
L
0
1
0
1
0
X
X
Continue Write Next
L
X
X
X
1
1
0
X
Continue Write Next
L
X
X
1
X
1
0
X
Suspend Write Current
L
X
X
X
1
1
1
X
Suspend Write Current
L
X
X
1
X
1
1
X
ZZ “Sleep”
None
H
X
X
X
X
X
X
X
Notes:
1. X = “Don't Care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BW_[1:0], and GW. See Write Cycle Description table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Write
X
X
X
X
X
X
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
Document #: 38-05247
Page 6 of 17