WCSS0418V1P Datasheet, PDF (5/17 Pages) Weida Semiconductor, Inc. – 256K x 18 Synchronous-Pipelined Cache RAM

WCSS0418V1P
Because the WCSS0418V1P is a common I/O device, the
Output Enable (OE) must be deasserted HIGH before present-
ing data to the DQ_[15:0] and DP_[1:0] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ_[15:0]
and DP_[1:0] are automatically three-stated whenever a write
cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE₁, CE₂, CE₃ are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW_[1:0]) are asserted active to conduct a write to
the desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to
A_[17:0] is loaded into the address register and the address ad-
vancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is con-
ducted, the data presented to the DQ_[15:0] and DP_[1:0] is written
into the corresponding address location in the RAM core. If a
byte write is conducted, only the selected bytes are written.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the WCSS0418V1P is a common I/O device, the
Output Enable (OE) must be deasserted HIGH before present-
ing data to the DQ_[15:0] and DP_[1:0] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ_[15:0]
and DP_[1:0] are automatically three-stated whenever a write
cycle is detected, regardless of the state of OE.
Burst Sequences
The WCSS0418V1P provides a two-bit wraparound counter,
fed by A_[1:0], that implements either an interleaved or linear
burst sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow
ZZ Mode Electrical Characteristics
Parameter
I_DDZZ
t_ZZS
t_ZZREC
Description
Snooze mode
standby current
Device operation to
ZZ
ZZ recovery time
Test Conditions
ZZ > V_DD − 0.2V
ZZ > V_DD − 0.2V
ZZ < 0.2V
a linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Interleaved Burst Sequence
First
Address
A_[1:0]
00
01
10
11
Second
Address
A_[1:0]
01
00
11
10
Third
Address
A_[1:0]
10
11
00
01
Fourth
Address
A_[1:0]
11
10
01
00
Linear Burst Sequence
First
Address
A_[1:0]
00
01
10
11
Second
Address
A_[1:0]
01
10
11
00
Third
Address
A_[1:0]
10
11
00
01
Fourth
Address
A_[1:0]
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CE₁, CE₂, CE₃, ADSP, and ADSC must remain inactive for the
duration of t_ZZREC after the ZZ input returns LOW.
Min.
2t_CYC
Max.
3
2t_CYC
Unit
mA
ns
ns
Document #: 38-05247
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