WCSS0418V1P Datasheet, PDF (13/17 Pages) Weida Semiconductor, Inc. – 256K x 18 Synchronous-Pipelined Cache RAM

Switching Waveforms (continued)
Pipeline Timing^{[18, 19]}
t_CH
CLK
t_AS
ADD
RD1 RD2 RD3 RD4
t_{ADS ADSC initiated Reads}
ADSC
ADSP
ADSP initiated Reads
t_CYC
t_ADH
ADV
CE₁
t_CES
WCSS0418V1P
t_CL
WD1 WD2 WD3 WD4
t_CEH
CE
WE
OE
t_WES
ADSP ignored
with CE₁ HIGH
t_WEH
t_CLZ
Data In/Out
t_CO
1a 2a 3a 4a
Out Out Out Out
Back to Back Reads
1a
2a
In
In
t_DOH
= DON’T CARE = UNDEFINED
Notes:
18. Device originally deselected.
19. CE is the combination of CE₂ and CE₃. All chip selects need to be active in order to select the device.
3a
In
4I_Dna(C)
t_CHZ
Document #: 38-05247
Page 13 of 17