WCSS0418V1P Datasheet, PDF (10/17 Pages) Weida Semiconductor, Inc. – 256K x 18 Synchronous-Pipelined Cache RAM

WCSS0418V1P
Switching Waveforms
Write Cycle Timing^{[14, 15]}
CLK
t_ADS
ADSP
ADSC
ADV
Single Write
t_CYC
t_ADH
t_ADS
t_ADH
t_ADVS
t_ADVH
Burst Write
t_CH
Pipelined Write
t_CL ADSP ignored with CE₁ inactive
ADSC initiated write
Unselected
t_AS
ADV Must Be Inactive for ADSP Write
ADD
WD1
WD2
t_AH
GW
WE
t_WH
t_WS
t_WH
t_WS
t_{CES tCEH}
CE₁
t_CES
CE₂
t_CEH
CE₁ masks ADSP
WD3
Unselected with CE₂
CE₃
t_CES
OE
t_CEH
t_DH
t_DS
Data ^High-Z
11aa
In
2a
2b
= UNDEFINED
2c
2d
3a
= DON’T CARE
Notes:
14. WE is the combination of BWE, BW_[1:0], and GW to define a write cycle (see Write Cycle Description table).
15. WDx stands for Write Data to Address X.
High-Z
Document #: 38-05247
Page 10 of 17