Z86129 Datasheet, PDF (8/50 Pages) Zilog, Inc. – NTSC LINE 21 DECIDER

Z86129/130/131
NTSC Line 21 Decoder
PRELIMINARY
Z86129/130/131 BLOCK DIAGRAM DESCRIPTION (Continued)
VCO and One Shot
All internal timing and synchronizing signals are derived
from the on-board 12 MHz VCO. Its output is the Dot Clk
signal used to drive the Horizontal and Vertical counter
chains and for display timing. The One Shot circuit
produces a horizontal timing signal derived from the
incoming video and qualified by the Copy Guard logic
circuits.
The VCO can be locked in phase to two different sources.
For television operation, where a good horizontal display
timing signal is available, the VCO is locked to the HIN
input through the action of the Phase Detector (PH2).
When a proper HIN signal is not available, such as in a
VCR, the VCO can be locked to the incoming video
through the Phase Detector (PH1). In this case the
frequency detector (FR) circuit is activated as required to
bring the VCO within the pull-in range of PH1.
Timing and Counting Circuits
The Dot Clk is first divided down to produce the character
timing clock CHAR CLK. This signal is then further divided
to generate the horizontal timing signals, H, 2H and
HSQR. These timing signals are used in the data output
(display) circuits.
The H signal is further divided in the LINE and FLD CNTR
to produce the various decodes used to establish vertical
lock and to time the display and control functions required
for proper operation. The H signal is also used to generate
the Smooth Scroll timing signal for display.
Command Processor
The Command Processor circuit controls the manipulation
of the data for storage and display. It processes the
Control Port input commands to determine the display
status desired and the data channel selected. During the
display time (lines 43-237), this information is used to
control the loading, addressing and clearing of the Display
RAM and the operations of the Character ROM and Output
Logic circuits.
During data recovery time (TV lines 21-42), the Command
Processor, in conjunction with the data recovery circuits,
recovers the XDS data and the data for the selected data
channel. Data is sent to the RAM for storage and display
and/or to the serial port, as appropriate. Where necessary,
the Command Processor converts the input data to the
appropriate form.
Output Logic (Z86129 only)
The output logic circuits operate together to generate the
output color signals RED, GREEN and BLUE and the Box
signal. When MONOchrome mode is selected all three
color outputs will carry the Luminance information. These
outputs are positive output logic signals.
The character ROM contains the dot pattern for all the
characters. The output logic provides the hardware
underline, graphics characters and the Italics slant
generator circuits. The smooth scroll display is achieved
by the smooth scroll counter logic controlling the
addressing of the Character ROM.
The V Lock circuits produce a noise free vertical pulse
derived from the horizontal timing signal. When the user
selects Video as the vertical lock source, the internal
synchronizing signals are phased up with the incoming
video by comparing the internally generated vertical pulse
to an input vertical pulse derived from the Comp Sync
signal provided by the Sync Slicer. In the vertical lock set
to VIN mode the VIN signal is used in place of the signal
derived from Comp Sync. In either case, when proper
phasing has been established, this circuit outputs the
LOCK signal which is used to provide additional noise
immunity to the slicing circuits.
The LOCKed state is established only after several
successive fields have occurred in which these two vertical
pulses remain in sync. Once LOCKed, the internal timing
will flywheel until such time as the two vertical pulses lose
coincidence for a number of consecutive fields. Until
LOCK is established, the decoder operates on a pulse for
pulse basis.
Decoder Control Circuit
The Decoder Control circuit block is the users
communications port. It converts the information provided
to the control port into the internal control signals required
to establish the operating mode of the decoder. This port
can be operated in one of two serial modes. The SMS pin
is used to establish the serial control mode to be used.
In the two wire (I²C) control mode, the Z86129/130/131 will
respond to its slave address for both the read and write
conditions. If the read bit is Low (indicating a WRITE
sequence) then the Z86129/130/131 will respond with an
acknowledge. The master should then send an address
byte followed by a data byte. If the read bit is High
(indicating a READ sequence) then the Z86129/130/131
will respond with an acknowledge followed by a status byte
then a data byte. Read data will only be available through
indirect addressing. Write addressing will have both
indirect and direct modes. The busy bit in the status byte
will indicate if the write operation has been completed or if
read data is available.
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