Z86129 Datasheet, PDF (21/50 Pages) Zilog, Inc. – NTSC LINE 21 DECIDER

PRELIMINARY
Z86129/130/131
NTSC Line 21 Decoder
The master's sequence for reading two data bytes (total Start Condition. A High-to-Low transition of SDA with
of three bytes including SSB) from the Z86129/130/131 is SCK High is a start condition which must precede any
given as:
other command.
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Start-Slave Address Read/Slave ACK-SS Byte/Master Stop Condition. A Low-to-High transition of SDA with
ACK-Byte (slave)/Master ACK-Byte (slave)/Master NACK- SCK High is a stop condition which terminates all
Stop
communications.
I2C-One Byte Write (Status Only)
STRT
SLAVE
ADDR
SERIAL
STATUS
STOP
(READ=29h)
(SSB)
NACK
I2C-Two Byte Read (Status & Data1)
STRT
SLAVE
ADDR
SERIAL
STATUS
READ
DATA1
STOP
(READ=29h)
(SSB)
NACK
I2C-Three Byte Read (Status, Data1, & Data2)
STRT
SLAVE
ADDR
SERIAL
STATUS
READ
DATA1
READ
DATA2
STOP
(READ=29h)
(SSB)
NACK
Note: In all I²C Read operations defined herein, the last byte read
from the Z86129/130/131 must be acknowledged by the master
with a NACK (Not ACKnowledge).
Figure 10. I²C Bus READ (Command)
Clock and Data Transitions. The SCK and SDA bus lines
are normally pulled High with a resistor. Data on the SDA
bus may only change during SCK Low time periods. Data
changes during SCK High periods will indicate a start or
stop condition as defined in Table 7.
Acknowledge. All address and data words are serially
transmitted to and from the Z86129/130/131 in eight bit
words. A ninth bit time is used for the acknowledge. The
acknowledging device does so by pulling the SDA bus Low
during the ninth bit. A Not Acknowledge (NACK) is given
by SDA=High during the ninth clock time.
t_F t_Hight_Low
t_R
SCK
t_SU.STA
t_HD.STA
SDA (IN)
t_AA
t_{HD.DAT tSU.DAT}
t_DH
t_SU.STO
t_BUF
SDA (OUT)
Figure 11. I²C Serial Timing
Symbol
f_SCK
t_LOW
t_High
t_R
t_F
t_AA
t_BUF
t_HD.STA
t_SU.STA
t_HD.DAT
t_SU.DAT
t_SU.STO
t_DH
t_I
Table 7. I²C Serial Timing Min/max
Parameter
Min
Clock Frequency
Clock Pulse Width Low
4.7
Clock Pulse Width High
4.0
SDA and SCL Rise Time
–
SDA and SCL Fall Time
–
Clock Low to Data Out Valid
0.1
Bus Free Time
4.7
Start Hold Time
4.0
Start Set-up Time
4.7
Data In Hold Time
0
Data In Set-up Time
250
Stop Set-up Time
4.7
Data Out Hold Time
100
Input Filter Time Constant
Max
100
–
–
1.0
300
3.5
–
–
–
–
–
–
–
100
Units
kHz
µs
µs
µs
ns
µs
µs
µs
µs
µs
ns
µs
ns
ns
DS96TEL0200
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