Z86129 Datasheet, PDF (30/50 Pages) Zilog, Inc. – NTSC LINE 21 DECIDER

Z86129/130/131
NTSC Line 21 Decoder
PRELIMINARY
INTERNAL REGISTERS (Continued)
D₅-D₇-s₀-s₂. Selects a set of secondary parameters,
tabulated below, to be used in filtering the XDS data when
XDS recovery has been enabled.
D₃-dLOK. Active High, indicating that the state of the
LOCK signal has changed. The SS register must be read
to determine the current state.
Table 13. XDS Secondary Filter Settings
Secondary Filter
Filter Value (s0:s2)
All
0h
Time Information
1h
In Band Only
2h
Program Rating (Note #4)
3h
VCR Information
4h
Reserved
5h
Reserved
6h
Reserved
7h
Notes:
1. Setting this register to 00h turns XDS data recovery off.
Setting bits D₀ through D₄ enables XDS data recovery for
the Classes selected as qualified by the Secondary Filter
(bits D₅-D₇). If Bits D₀-D₄ are all set to 1, all Classes of XDS
data will be output (even Reserved and Undefined).
2. The Time Information Only selection includes the Time of
Day (TOD) and Local Time Zone (LTZ) packets.
3. VCR Information will select TOD, LTZ, Net ID, Local Call
Letters, Impulse Capture, Tape Delay, Composite 2 and
Out of Band Channel Number packets for recovery.
4. Program rating filter available on Z86129 and Z86130
only.
Interrupt Request Register Address = 06h
Bit D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀
dTXT dCAP dXDS dSCH dLOK EOF DLE res
R/W R/W R/W R/W R/W R R R
D₄-dSCH. Active High, indicating that a change in selected
channel activity has occurred. The Line 21 Activity register
must be read in order to determine if the selected data
channel is active.
D₅-dXDS. Active High, indicating that a change in XDS
activity has occurred. The Line 21 Activity register must be
read to determine if XDS data is active.
D₆-dCAP. Active High, indicating that a change in a
caption data channel activity has occurred. The Caption
Activity Register (Address 08h) must be read to determine
exactly which caption channels are now active.
D₇-dTXT. Active High, indicating that a change in a TEXT
data channel activity has occurred. The Caption Activity
Register (Address 08h) must be read to determine exactly
which TEXT channels are now active.
Note: Except as noted for the case of D1 and D2 above,
the master device must write a 1 to the appropriate bit in
the Interrupt Request Register to clear the Interrupt.
Writing a 1 to any valid bit position the Interrupt Request
Register is equivalent to CLEARing a interrupt request on
that bit.
Interrupt Mask Register Address = 07h
Bit D₇
D₆ D₅ D₄ D₃
dTXT dCAP dXDS dSCH dLOK
R/W R/W R/W R/W R/W
D₂
EOF
R/W
D₁
DLE
R/W
D₀
DAV
R/W
Figure 26. Interrupt Mask Register Address = 07h
Figure 25. Interrupt Request Register (Address = 06h)
D₀-res. Reserved.
D₁-DLE. Active High, indicating that the data line has
ended. This bit will clear in each field a few lines after row
15.
This register identifies which activities in the Interrupt
Request Register will be used to cause an interrupt.
Setting a bit to a 1 enables the interrupt when the
corresponding event becomes active. Setting all bits of this
register to zero disables interrupts.
D₂-EOF. Active High, indicating that the video signal is
currently at the end of a field. This bit will clear in each field
a few lines after row 15.
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