Z86129 Datasheet, PDF (22/50 Pages) Zilog, Inc. – NTSC LINE 21 DECIDER

Z86129/130/131
NTSC Line 21 Decoder
PRELIMINARY
SERIAL COMMUNICATIONS INTERFACE (Continued)
SPI Bus Operation
When the SMS pin is High the Z86129/130/131 will be in
the SPI serial control mode. The clock line should be tied
to the SCK pin. The DATA IN signal and DATA OUT signal
from the master device should be connected to the SDA
and SDO pins respectively. The SEN pin is used to select
the Z86129/130/131 when there are multiple peripherals
on the bus.
see if the DAV bit is set. Both of these bits are contained in
the Serial Status (SS) register. Writing to the
Z86129/130/131 will concurrently output the contents of
the SS register, MSB first, unless other data is being
output as a result of one of the READ commands. If it is
desired to read the SS without executing a command, the
NOP command can be written at any time, even if the
serial status RDY bit is not set.
As noted above, when both the SMS and SEN pins are
Low, the part is in the RESET state. When the SPI bus is
used in a dedicated fashion between the master and the
Z86129/130/131, both the SEN and SMS pins would be
tied High. The RESET function would require that both of
these pins be tied to the NRESET signal. To ensure
synchronization, the master should send the serial
synchronization signal after the reset is released.
When the SPI mode is used in a multiple peripheral
environment, the SEN pin is used as the Z86129/130/131
enable signal. SMS could then be used for the NRESET
signal as long as reset was only applied while SEN was
Low. In this case, there would be no need for the master to
send a serial synchronization string after reset if there was
at least 100 ns between the end of reset and the start of
port enable.
A command string can be interrupted at any time and the
port resynchronized by sending the Serial Sync signal or
by the rising edge of SEN.
The SPI bus is a three wire bus when used in a dedicated
manner between the Z86129/130/131 and the master
device. If other peripherals are connected to the bus, then
the SEN pin must be used to place this device on the bus
at the appropriate time. When SEN is Low, the SDO pin
will be tri-state and transitions on the SCK and SDA pins
will be ignored.
If data output is not required from the Z86129/130/131,
then control can be accomplished using only the SCK and
SDA pins. Since this type of operation precludes the ability
to check the RDY bit, it is very important that commands
be spaced by at least two frames (133 µsec) to ensure that
one command has been executed before initiating
another.
The bus is controlled by the master device, which
generates the serial clock (SCK) and initiates all actions.
Clocking data in on SDA will simultaneously produce data
out on SDO. The master should always check for the
appropriate handshake signal before executing any
command other than NOP.
Writing to the part requires that the RDY bit be set while
reading from the part requires checking the SS register to
The RDY status bit is driven onto the SDO pin between
command transmissions. The controlling MCU can test the
state of this pin without clocking in order to determine if
subsequent serial transfers are possible. The DAV bit can
only be checked by outputting the contents of the SS
register.
Writing to the SPI Bus
All write commands are either one or two byte commands.
The number of data bytes to be received by the
Z86129/130/131 is inherent in the command. If the master
writes more bytes than expected, the command may be
overwritten or corrupted by the extraneous bytes.
A write to the Z86129/130/131 should always be preceded
by executing a Status read to verify that the device is
ready. The serial status is output by the device concurrent
with the input of any command byte. If the RDY bit of the
serial status register is set, the master device can write a
new command.
The command and data bytes are written MSB first. The
first byte of a two byte command is sent first. The bits are
clocked into the Z86129/130/131 by placing the data on
the SDA input and bringing SCK High.
Reading Data Using the SPI Bus
With the exception of the SS read, each read operation
must be set up before the data can actually be read from
the serial output registers of the device. Data is set up for
a read operation either automatically or manually. XDS
data is set up for READ automatically upon recovery by
setting a valid XDS FILTER register selection. All other
data read operations must be set up manually, using the
READ SELECT commands RDS1 and RDS2. These
commands load the selected data byte or pair of bytes into
the serial output registers, set the SS register RD2 bit
according to the number of data bytes requested and set
the serial status DAV bit to indicate availability of data.
The Z86129/130/131 SPI Bus supports two and three byte
read sequences. In SPI mode, the SS must be read before
a read sequence is started so that the DAV and RD2 bits
can be checked. The number of data bytes available is
indicated by the state of the RD2 bit. The special command
READ1 or READ2 is then used to read the one or two
available data bytes. The serial status is clocked out during
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