Z86129 Datasheet, PDF (7/50 Pages) Zilog, Inc. – NTSC LINE 21 DECIDER

PRELIMINARY
Z86129/130/131
NTSC Line 21 Decoder
Pins With External Components
Power Supply
CSync (Pin 8). Sync slice level. A 0.1 µF capacitor must V_DD (Pin 12). The voltage on this pin is nominally 5.0 Volts
1 ^{be tied between this pin and analog ground VSS(A). This and may range between 4.75 to 5.25 Volts with respect to}
capacitor stores the sync slice level voltage.
the V_SS pins.
LPF (Pin 9). Loop Filter. A series RC low-pass filter must
be tied between this pin and analog ground V_SS(A). There
must also be second capacitor from the pin to V_SS(A).
Values for the three parts to be specified at a later date.
RREF (Pin 10). Reference setting resistor. Resistor must
be 10 kohms, ±2%.
V_SS (Pins 1, 11). These pins are the lowest potential
power pins for the analog and digital circuits. They are
normally tied to system ground. Note: The recommended
printed circuit pattern for implementing the power
connection and critical components will be supplied at a
later date.
Z86129/130/131 BLOCK DIAGRAM DESCRIPTION
The Z86129 is designed to process both fields of Line 21
of the television VBI and provide the functional
performance of a Line 21 Closed-Caption decoder and
Extended Data Service decoder. It requires two input
signals, Composite Video and a horizontal timing signal
(HIN), and several passive components for proper
operation. A vertical input signal is also required if OSD
display mode is desired when no video signal is present.
The Decoder performs several functions, namely
extraction of the data from Line 21, separation of the
normal Line 21 data from the XDS data, on-screen display
(Z86129 only) of the selected data channel and outputting
of the XDS data through the serial communications
channel.
Input Signals
The Composite Video input should be a signal which is
nominally 1.0 Volt p-p with sync tips negative and band
limited to 600 kHz. The Z86129 will operate with an input
level variation of ±3 dB.
The HIN input signal is required to bring the VCO close to
the desired operating frequency. It must be a CMOS level
signal. The HIN signal can have positive or negative
polarity and is only required to be within 3% of the standard
H frequency. When configured for EXT HLK operation, this
signal should correspond to the H Flyback signal.
The timing difference between HIN rising edge and the
leading edge of composite sync (of VIDEO input) is one of
the factors that will affect the horizontal position of the
display. Any shift resulting from the timing of this signal can
be compensated for with the horizontal timing value in the
H Position register.
Video Input Signal Processing
The Comp Video input is AC coupled to the device where
the sync tip is internally clamped to a fixed reference
voltage by means of a dual clamp. Initially, the unlocked
signal is clamped using a simple clamp. Improved impulse
noise performance is then achieved after the internal sync
circuits lock to the incoming signal. Noise rejection is
obtained by making the clamp operative only during the
sync tip. The clamped composite video signal is fed to both
the Data Slicer and Sync Slicer blocks.
The Data Slicer generates a clean CMOS level data signal
by slicing the signal at its midpoint. The slice level is
established on an adaptive basis during Line 21. The
resultant value is stored until the next occurrence of that
Line 21. A high level of noise immunity is achieved by
using this process.
The Sync Slicer processes the clamped Comp Video
signal to extract Comp Sync. This signal is used to lock the
internally generated sync to the incoming video when the
video lock mode of operation has been enabled. Sync
slicing is performed in two steps. In the non-locked mode,
the sync is sliced at a fixed offset level from the sync tip.
When proper lock operation has been achieved, the slice
level voltage switches from a fixed reference level to an
adaptive level. The slice level is stored on the sync slice
capacitor, CSYNC.
The Data Clock Recovery circuit operates in conjunction
with the Digital H Lock circuit. They produce a 32H clock
signal (DCLK) that is locked in phase to the clock run-in
burst portion of the sliced data obtained from the Data
Slicer. When Line 21 code appears, DCLK phase lock is
achieved during the clock run-in burst and used to reclock
the sliced data. Once phase lock is established it is
maintained until a change in video signal occurs.
The Digital H Lock circuit produces the video timing gates,
PG, STG, and so on, which are locked in phase with
HSYNC, the video timing signal, no matter which H lock
mode is used in the display generation circuits. This
independent phase lock loop is able to respond quickly to
changes in video timing, without concern for display
stability requirements.
DS96TEL0200
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