Z86129 Datasheet, PDF (5/50 Pages) Zilog, Inc. – NTSC LINE 21 DECIDER

PRELIMINARY
Z86129/130/131
NTSC Line 21 Decoder
ELECTRICAL CHARACTERISTICS
Non Standard Video Signals must have the following characteristics:
1
Parameter
Conditions
Sync Amplitude
200 mV minimum
Vertical Pulse Width
3H ±0.5H
Vertical Pulse Tilt
20 mV maximum
H Timing
Phase Step (Head Switch) ±10 µs maximum
Fh Deviation (long term) ±0.5% maximum
Fh p-p Deviation (short term) ±0.3% maximum
Vertical Sync Signal
The internal sync circuits will lock to all 525 or 625 line signals having a vertical
sync pulse that meets the following conditions:
1. It is at least 2H wide.
2. It starts at the proper 2H boundary for its field.
3. If equalizing pulse serrations are present, they must be less than 0.125H in
width.
Minimum Signal-to-Noise
The Z86129/130/131 will function down to a 25 dB signal-to-noise ratio (CCIR
weighted) with one error per row or better at that level.
Ratio to Composite Video
Input
Horizontal Signal Input (preferably H Flyback)
Parameter
Amplitude
Video Lock Mode:
HIN Lock Mode:
Conditions
CMOS level signal where Low <= 0.2 V_CC
Polarity
Frequency
Any
15,734.263 Hz ±3%
Polarity
Any
Frequency
Same as Display Horizontal Flyback Pulse (HFB) pulse
Line 21 Input Parameters (at 1.0V p-p)
Note: Line 21 must be in its proper position to the leading edge of the Vertical Sync signal.
Parameter
Cod Amplitude
Code Zero Level
Start of Code
Start of Data
Conditions
50 IRE
5 IRE, +15 IRE relative to Back Porch
10.5 ±0.5 µs, (Measured from the midpoint of the falling edge of the last clock run-in cycle
to the midpoint of the rising edge of the start bit.)
3.972 µs, –0.00 µsec, +0.30 µs (Measured from the midpoint of the falling edge of the last
clock run-in cycle to the midpoint of the rising edge of the start bit.
Timing Signals
Parameter
Dot
Dot Period
Character Cell Width
Width of Row (Box)
Width of Row (Char)
Horizontal Display Timing
Conditions
768 x FH = 12.0839 MHz
82.75 ns
1.324 µs (tH/48)
45.018 µs (34 chars = 17/24 x tH
42.370 µs (32 chars = 2/3 x tH
The timing of the output signals Box and RGB have been set to make a centered display.
The positioning of these outputs can be adjusted in 330 ns increments by writing a new
value to the Z86129 H Position Register (Address = 02h).
DS96TEL0200
5