Z86129 Datasheet, PDF (29/50 Pages) Zilog, Inc. – NTSC LINE 21 DECIDER

PRELIMINARY
Z86129/130/131
NTSC Line 21 Decoder
D₆-ODRP. Selects Drop Shadow or Full Box in the OSD Line 21 Activity Register Address = 04h
and XDS display modes: High = DROP SHADOW and
Low = BOX. The default is High.
Bit D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀
1
D₇-O15. Selects the number of TV lines per character row
res res res res res res XDS SCH
in the OSD and XDS display modes: High = 15 lines/row
and Low = 13 lines/row. The default is High.
RR
H Position Register Address = 02h
Figure 23. Line 21 Activity Register (Address = 04h)
Bit D₇ D₆
BLUBX HPO
R/W R/W
D₅
h₅
R/W
D₄
h₄
R/W
D₃
h₃
R/W
D₂
h₂
R/W
D₁
D₀
h₁ h₀
R/W R/W
D₀-SCH. Indicates data being processed in the Data
Channel selected for display. Will become inactive if no
data is received for the selected channel within the
previous 16 seconds: High = Active, Low = Inactive. The
reset state is Low.
Figure 21. H Position Register (Address = 02h)
D₀-D₅-h₀-h₅. Used to set the Horizontal Timing of the
display. The default value in this register is 26h. Each
count change represents an incremental timing change of
330 ns. Decreasing the value of this field moves the
display to the RIGHT. Conversely, increasing the value of
this field moves the display to the LEFT.
D₆-HPO. Set the polarity to be used for locking to the HIN
signal when in the EXT HLK mode: Low = Rising Edge,
High = Falling Edge. The default is Low.
D₇-BLUBX. Designates color of BOX: High = Blue Box and
Low = Black Box. The default is Low.
Text Position Register Address = 03h
Bit D₇
y₃
R/W
D₆
y₂
R/W
D₅
y₁
R/W
D₄
y₀
R/W
D₃
x₃
R/W
D₂
x₂
R/W
D₁
x₁
R/W
D₀
x₀
R/W
Figure 22. Text Position Register (Address = 03h)
D₀-D₃-x₀-x₃. Sets the Number Of Rows in the TEXT
display. The default is 15 rows.
D₄-D₇-y₀-y₃. Sets the Base Row of the TEXT display.
The default value in this register is set to FFh, which
produces a 15-row display with base row 15. Entering a
new value in this register can alter the size and placement
of the TEXT display. For example, to produce an 8 row
TEXT display with a base row of 12, this register should be
set to C8h. If the value of the x and y bits result in a display
where TEXT rows are off the top of the screen, then the
first row of the TEXT display will start in row 1 and have the
number of rows determined by the x value.
D₁-XDS. Indicates XDS data is being processed. Will
become inactive if no XDS data is received within the
previous 16 seconds: High = Active, Low = Inactive. The
reset state is Low.
D₂-D₇. Reserved.
XDS Filter Register Address = 05h
Bit D₇
s₂
R/W
D₆
s₁
R/W
D₅
s₀
R/W
D₄
PUBL
R/W
D₃
D₂
D₁
D₀
MISC CHAN FUTR CURR
R/W R/W R/W R/W
Figure 24. XDS Filter Register (Address = 05h)
D₀-CURR. Selects Current Class packets for output
through the Serial Control port when XDS recovery has
been enabled.
D₁-FUTR. Selects Future Class packets for output through
the Serial Control port when XDS recovery has been
enabled.
D₂-CHAN. Selects Channel Information Class packets for
output through the Serial Control port when XDS recovery
has been enabled.
D₃-MISC. Selects Miscellaneous Class packets for output
through the Serial Control port when XDS recovery has
been enabled.
D₄-PUBL. Selects Public Service Class packets for output
through the Serial Control port when XDS recovery has
been enabled.
DS96TEL0200
29