EZ80F917050SBCG Datasheet, PDF (8/30 Pages) Zilog, Inc. – Factory-default operating clock frequency at 50 MHz

Zdots^® SBC for eZ80AcclaimPlus!^™ Connectivity ASSP
Product Specification
4
Pin Description
Peripheral Bus Connector
Figure 2 displays the pin layout of the 60-pin Peripheral Bus Connector (JP1) of the
Zdots^®. Table 1 on page 5 describes the pins and their functions.
Figure 2. Zdots Peripheral Bus Connector Pin Configuration—JP1
Note: All signals with an overline are active Low. For example, B/W, for which WORD
is active Low, and B/W, for which BYTE is active Low.
PS026102-1207
Pin Description