EZ80F917050SBCG Datasheet, PDF (18/30 Pages) Zilog, Inc. – Factory-default operating clock frequency at 50 MHz

Zdots^® SBC for eZ80AcclaimPlus!^™ Connectivity ASSP
Product Specification
14
going into High-Z mode, that is, after the end of the eZ80F91 Read access to Flash, it
takes 8.8 ns+25 ns = 33.8 ns before Flash stops driving the data bus. At this point, the
eZ80F91 device is already well into the next bus cycle.
Consider the next cycle to be Memory Write. During the Memory Write cycle, data (out-
put) from the eZ80F91 device is valid not later than T3 = 7.5 ns, and the Write pulse is
asserted not later than 4.5 ns after the falling edge of the Clock (14.5 ns from the rising
edge if Clock is 50 MHz). It means that during T_CON = (33.8 ns – 7.5 ns) = 26.3 ns; two
devices drive the common Data Bus—the eZ80F91 device and Flash. In turn, data that is
being written during the Write operation might be corrupted. The part used to isolate a
slow Flash data bus from a fast eZ80F91 bus has 5.5 ns turn-off time, which reduces 25 ns
part of the T_CON to 5.5 ns. As a result, bus contention still occurs, but its duration is not
26.3 ns, as described in the following equation:
Time of contention = (8.8 ns-7.5 ns + 5.5 ns) = 6.8 ns
Data being written is not corrupted because the Write pulse is not yet asserted.
T6
Clock
-CS0
F91 Data
Bus
T3
Data IN
Data OUT
-RD
FLash
Data Bus
-CS1
-WR
Bus contention
Tod
T4
Figure 4. Bus Contention without the Zdots Fast Buffer Feature
PS026102-1207
Onboard Component Description