EZ80F917050SBCG Datasheet, PDF (20/30 Pages) Zilog, Inc. – Factory-default operating clock frequency at 50 MHz

Zdots^® SBC for eZ80AcclaimPlus!^™ Connectivity ASSP
Product Specification
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disabled by setting PD2 (IR_SD) High or by pulling the DIS_IRDA pin on the I/O
connector Low. The shutdown is used for power savings. To enable the IrDA transceiver,
DIS_IRDA is left floating and PD2 is set to Low.
Reset Generator
The onboard Reset Generator Chip performs reliable Power-On Reset. The chip generates
a reset pulse with a duration of 200 ms if the power supply drops below 2.93 V. This reset
pulse ensures that the board always starts in a defined condition. The RESET pin on the
I/O connector reflects the status of the RESET line. It is a bidirectional pin for resetting
external peripheral components or for resetting the Zdots with a low-impedance output
(for example, a 100 Ω push button).
Serial Interface Ports
The CPU contains two UARTs with programmable baud rate generators. UART0 is con-
nected to GPIO PD[0:7] on the I/O connector. UART1 is connected to GPIO PC[0:7] on
the I/O connector.
Note: Do not connect an RS-232 interface without level shifters. There are no
RS-232 level shifters on the Zdots.
Physical Dimensions
The footprint of the Zdots PCB is 63.5 mm x 78.7 cm. With an RJ-45 Ethernet connector,
the overall height is 25 mm, see Figure 5 on page 17.
PS026102-1207
Onboard Component Description